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[Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less |
Date: |
Wed, 7 Sep 2016 20:29:16 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.
Instead, pass the releavant opcode bits via the error_code.
There are a couple of cases of alignment interrupts that won't set
anything, the ones coming from access to direct store segments, but
that doesn't happen in practice, nobody used direct store segments
and they are gone from newer chips.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 9 +++++----
target-ppc/translate.c | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 882d529..04ed4da 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* XXX: this is false */
/* Get rS/rD and rA from faulting opcode */
- /* Broken for LE mode */
- env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip)
- & 0x03FF0000) >> 16;
+ /* Note: the opcode fields will not be set properly for a direct
+ * store load/store, but nobody cares as nobody actually uses
+ * direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index bebd1cc..6bb0ba9 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2417,7 +2417,7 @@ static inline void gen_check_align(DisasContext *ctx,
TCGv EA, int mask)
tcg_gen_andi_tl(t0, EA, mask);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
- t2 = tcg_const_i32(0);
+ t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
gen_update_nip(ctx, ctx->nip - 4);
gen_helper_raise_exception_err(cpu_env, t1, t2);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-ppc] [PULL 11/64] target-ppc: add cmpeqb instruction, (continued)
- [Qemu-ppc] [PULL 11/64] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 10/64] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 02/64] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less,
David Gibson <=
- [Qemu-ppc] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 41/64] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 39/64] ppc: Speed up dcbz, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 58/64] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 62/64] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 45/64] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 32/64] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/07