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[Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping |
Date: |
Wed, 7 Sep 2016 20:29:34 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
The current mapping, while correct for the base ports (which is all the
driver uses these days), is wrong for the extended registers.
I suspect the bugs come from incorrect tables in the CHRP IO Ref document,
I have verified the new values here match Apple's MacTech.pdf.
Note: Nothing that I know of actually uses these registers so it's not a
huge deal, but this patch has the added advantage of adding comments to
document what the registers are.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/misc/macio/macio.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c
index be03926..5d57f45 100644
--- a/hw/misc/macio/macio.c
+++ b/hw/misc/macio/macio.c
@@ -89,22 +89,16 @@ static void macio_escc_legacy_setup(MacIOState *macio_state)
MemoryRegion *bar = &macio_state->bar;
int i;
static const int maps[] = {
- 0x00, 0x00,
- 0x02, 0x20,
- 0x04, 0x10,
- 0x06, 0x30,
- 0x08, 0x40,
- 0x0A, 0x50,
- 0x60, 0x60,
- 0x70, 0x70,
- 0x80, 0x70,
- 0x90, 0x80,
- 0xA0, 0x90,
- 0xB0, 0xA0,
- 0xC0, 0xB0,
- 0xD0, 0xC0,
- 0xE0, 0xD0,
- 0xF0, 0xE0,
+ 0x00, 0x00, /* Command B */
+ 0x02, 0x20, /* Command A */
+ 0x04, 0x10, /* Data B */
+ 0x06, 0x30, /* Data A */
+ 0x08, 0x40, /* Enhancement B */
+ 0x0A, 0x50, /* Enhancement A */
+ 0x80, 0x80, /* Recovery count */
+ 0x90, 0x90, /* Start A */
+ 0xa0, 0xa0, /* Start B */
+ 0xb0, 0xb0, /* Detect AB */
};
memory_region_init(escc_legacy, OBJECT(macio_state), "escc-legacy", 256);
--
2.7.4
- [Qemu-ppc] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, (continued)
- [Qemu-ppc] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 41/64] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 55/64] ppc: Fix macio ESCC legacy mapping,
David Gibson <=
- [Qemu-ppc] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 39/64] ppc: Speed up dcbz, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 58/64] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 62/64] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 45/64] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 32/64] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 08/64] target-ppc: add modulo dword operations, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 34/64] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/07
- [Qemu-ppc] [PULL 30/64] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/07