Re: [Qemu-ppc] [PATCH v3 04/10] ppc/pnv: add a PIR handler to PnvChip

[Benjamin Herrenschmidt]

On Wed, 2016-09-21 at 11:29 +1000, David Gibson wrote:
> On Thu, Sep 15, 2016 at 02:45:54PM +0200, Cédric Le Goater wrote:
> > 
> > P9 and P8 have some differences in the CPU PIR encoding.
> 
> The thread id isn't in the PIR at all?

Yes it is. Though on P9 there could be different encodings depending on
some kind of "mode" I can't quite yet get into details about.

Cheers,
Ben.

> > 
> > 
> > Signed-off-by: Cédric Le Goater <address@hidden>
> > ---
> >  hw/ppc/pnv.c         | 14 ++++++++++++++
> >  include/hw/ppc/pnv.h |  1 +
> >  2 files changed, 15 insertions(+)
> > 
> > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> > index ec7dd6ac5ea1..f4c125503249 100644
> > --- a/hw/ppc/pnv.c
> > +++ b/hw/ppc/pnv.c
> > @@ -238,6 +238,16 @@ static void ppc_powernv_init(MachineState
> > *machine)
> >      g_free(chip_typename);
> >  }
> >  
> > +static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t
> > core_id)
> > +{
> > +    return (chip->chip_id << 7) | (core_id << 3);
> > +}
> > +
> > +static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t
> > core_id)
> > +{
> > +    return (chip->chip_id << 8) | (core_id << 2);
> > +}
> > +
> >  /* Allowed core identifiers on a POWER8 Processor Chip :
> >   *
> >   * <EX0 reserved>
> > @@ -273,6 +283,7 @@ static void
> > pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
> >      k->chip_type = PNV_CHIP_POWER8E;
> >      k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1
> > */
> >      k->cores_mask = POWER8E_CORE_MASK;
> > +    k->core_pir = pnv_chip_core_pir_p8;
> >      dc->desc = "PowerNV Chip POWER8E";
> >  }
> >  
> > @@ -292,6 +303,7 @@ static void
> > pnv_chip_power8_class_init(ObjectClass *klass, void *data)
> >      k->chip_type = PNV_CHIP_POWER8;
> >      k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
> >      k->cores_mask = POWER8_CORE_MASK;
> > +    k->core_pir = pnv_chip_core_pir_p8;
> >      dc->desc = "PowerNV Chip POWER8";
> >  }
> >  
> > @@ -311,6 +323,7 @@ static void
> > pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
> >      k->chip_type = PNV_CHIP_POWER8NVL;
> >      k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0
> > */
> >      k->cores_mask = POWER8_CORE_MASK;
> > +    k->core_pir = pnv_chip_core_pir_p8;
> >      dc->desc = "PowerNV Chip POWER8NVL";
> >  }
> >  
> > @@ -330,6 +343,7 @@ static void
> > pnv_chip_power9_class_init(ObjectClass *klass, void *data)
> >      k->chip_type = PNV_CHIP_POWER9;
> >      k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
> >      k->cores_mask = POWER9_CORE_MASK;
> > +    k->core_pir = pnv_chip_core_pir_p9;
> >      dc->desc = "PowerNV Chip POWER9";
> >  }
> >  
> > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> > index cfc32586320f..2bd2294ac2a3 100644
> > --- a/include/hw/ppc/pnv.h
> > +++ b/include/hw/ppc/pnv.h
> > @@ -58,6 +58,7 @@ typedef struct PnvChipClass {
> >      uint64_t     cores_mask;
> >  
> >      void (*realize)(PnvChip *dev, Error **errp);
> > +    uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
> >  } PnvChipClass;
> >  
> >  #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
>