[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 06/45] target-ppc: add vector bit permute doubleword in
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction |
Date: |
Fri, 23 Sep 2016 17:14:42 +1000 |
From: Rajalakshmi Srinivasaraghavan <address@hidden>
Add vbpermd instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 20 ++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 1 +
target-ppc/translate/vmx-ops.inc.c | 1 +
4 files changed, 23 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index b11c39a..e148861 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -333,6 +333,7 @@ DEF_HELPER_2(vpopcntb, void, avr, avr)
DEF_HELPER_2(vpopcnth, void, avr, avr)
DEF_HELPER_2(vpopcntw, void, avr, avr)
DEF_HELPER_2(vpopcntd, void, avr, avr)
+DEF_HELPER_3(vbpermd, void, avr, avr, avr)
DEF_HELPER_3(vbpermq, void, avr, avr, avr)
DEF_HELPER_2(vgbbd, void, avr, avr)
DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 4d1582d..b12af95 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1128,12 +1128,32 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a, ppc_avr_t *b,
#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
+#define VBPERMD_INDEX(i) (i)
#define VBPERMQ_DW(index) (((index) & 0x40) != 0)
+#define EXTRACT_BIT(avr, i, index) (extract64((avr)->u64[i], index, 1))
#else
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[15-(i)])
+#define VBPERMD_INDEX(i) (1 - i)
#define VBPERMQ_DW(index) (((index) & 0x40) == 0)
+#define EXTRACT_BIT(avr, i, index) \
+ (extract64((avr)->u64[1 - i], 63 - index, 1))
#endif
+void helper_vbpermd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i, j;
+ ppc_avr_t result = { .u64 = { 0, 0 } };
+ VECTOR_FOR_INORDER_I(i, u64) {
+ for (j = 0; j < 8; j++) {
+ int index = VBPERMQ_INDEX(b, (i * 8) + j);
+ if (index < 64 && EXTRACT_BIT(a, i, index)) {
+ result.u64[VBPERMD_INDEX(i)] |= (0x80 >> j);
+ }
+ }
+ }
+ *r = result;
+}
+
void helper_vbpermq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index 982feff..cb89330 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -792,6 +792,7 @@ GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM(vbpermd, 6, 23);
GEN_VXFORM(vbpermq, 6, 21);
GEN_VXFORM_NOA(vgbbd, 6, 20);
GEN_VXFORM(vpmsumb, 4, 16)
diff --git a/target-ppc/translate/vmx-ops.inc.c
b/target-ppc/translate/vmx-ops.inc.c
index 7172cdc..a944671 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -261,6 +261,7 @@ GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE,
PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_300(vbpermd, 6, 23),
GEN_VXFORM_207(vbpermq, 6, 21),
GEN_VXFORM_207(vgbbd, 6, 20),
GEN_VXFORM_207(vpmsumb, 4, 16),
--
2.7.4
- [Qemu-ppc] [PULL 30/45] target-ppc: consolidate store conditional, (continued)
- [Qemu-ppc] [PULL 30/45] target-ppc: consolidate store conditional, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 25/45] target-ppc: consolidate store operations, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 35/45] spapr: Introduce sPAPRCPUCoreClass, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 05/45] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 32/45] target-ppc: add lxsi[bw]zx instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 34/45] target-ppc: implement darn instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 44/45] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction,
David Gibson <=
- [Qemu-ppc] [PULL 28/45] target-ppc: consolidate load with reservation, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 29/45] target-ppc: move out stqcx impementation, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 23/45] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 07/45] target-ppc: add vector permute right indexed instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 38/45] target-ppc: tlbie/tlbivax should have global effect, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 42/45] ppc/kvm: Mark 64kB page size support as disabled if not available, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 41/45] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 33/45] target-ppc: add stxsi[bh]x instruction, David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 39/45] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/23
- [Qemu-ppc] [PULL 45/45] spapr_pci: Add numa node id, David Gibson, 2016/09/23