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[Qemu-ppc] [PATCH v6 07/10] ppc/pnv: link the CPUs to the machine XICS
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v6 07/10] ppc/pnv: link the CPUs to the machine XICS |
Date: |
Tue, 8 Nov 2016 09:08:07 +0100 |
This also maps all the chip container ICP region and the threads ICP
subregions. The device tree is populated accordingly.
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v5:
- reworked to fit new model
Changes since v4:
- changed the calculation of the number of ICPs to use smp_threads
- added the mapping of the ICP subregions per thread
hw/ppc/pnv.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/pnv_core.c | 12 ++++++++----
2 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 474e791bbe50..45a9236e10fe 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -33,6 +33,7 @@
#include "qemu/cutils.h"
#include "qapi/visitor.h"
+#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/isa/isa.h"
@@ -214,6 +215,47 @@ static void powernv_create_core_node(PnvChip *chip,
PnvCore *pc, void *fdt)
servers_prop, sizeof(servers_prop))));
}
+static void powernv_populate_icp(PnvChip *chip, void *fdt, int offset,
+ uint32_t pir, uint32_t count)
+{
+ uint64_t addr;
+ char *name;
+ const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
+ uint32_t irange[2], i, rsize;
+ uint64_t *reg;
+
+ /*
+ * TODO: add multichip ICP BAR
+ */
+ addr = PNV_ICP_BASE(chip) | (pir << 12);
+
+ irange[0] = cpu_to_be32(pir);
+ irange[1] = cpu_to_be32(count);
+
+ rsize = sizeof(uint64_t) * 2 * count;
+ reg = g_malloc(rsize);
+ for (i = 0; i < count; i++) {
+ reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
+ reg[i * 2 + 1] = cpu_to_be64(0x1000);
+ }
+
+ name = g_strdup_printf("address@hidden"PRIX64, addr);
+ offset = fdt_add_subnode(fdt, offset, name);
+ _FDT(offset);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
+ _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
+ _FDT((fdt_setprop_string(fdt, offset, "device_type",
+ "PowerPC-External-Interrupt-Presentation")));
+ _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
+ _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
+ irange, sizeof(irange))));
+ _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
+ _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
+ g_free(reg);
+}
+
static void powernv_populate_chip(PnvChip *chip, void *fdt)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
@@ -227,6 +269,10 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
powernv_create_core_node(chip, pnv_core, fdt);
+
+ /* Interrupt presentation controllers (ICP). One per thread. */
+ powernv_populate_icp(chip, fdt, 0, pnv_core->pir,
+ CPU_CORE(pnv_core)->nr_threads);
}
if (chip->ram_size) {
@@ -682,6 +728,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
error_propagate(errp, error);
return;
}
+ sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
/* Cores */
pnv_chip_core_sanitize(chip, &error);
@@ -696,6 +743,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
&& (i < chip->nr_cores); core_hwid++) {
char core_name[32];
void *pnv_core = chip->cores + i * typesize;
+ int j;
if (!(chip->cores_mask & (1ull << core_hwid))) {
continue;
@@ -719,6 +767,13 @@ static void pnv_chip_realize(DeviceState *dev, Error
**errp)
/* Each core has an XSCOM MMIO region */
pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid),
&PNV_CORE(pnv_core)->xscom_regs);
+
+ /* Each thread has a ICP MMIO region */
+ for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
+ memory_region_add_subregion(&chip->icp_mmio,
+ (pcc->core_pir(chip, core_hwid) + j) << 12,
+ &PNV_CORE(pnv_core)->icp_mmios[j]);
+ }
i++;
}
g_free(typename);
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 426b18b59ed8..9ee43d3f9010 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -25,6 +25,7 @@
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/xics.h"
static uint64_t pnv_core_icp_read(void *opaque, hwaddr addr, unsigned width)
{
@@ -165,7 +166,7 @@ static void powernv_cpu_reset(void *opaque)
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
+static void powernv_cpu_init(PowerPCCPU *cpu, XICSState *xics, Error **errp)
{
CPUPPCState *env = &cpu->env;
int core_pir;
@@ -185,6 +186,9 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
qemu_register_reset(powernv_cpu_reset, cpu);
+
+ /* xics_cpu_setup() assigns the CPU to the ICPState */
+ xics_cpu_setup(xics, cpu);
}
/*
@@ -232,7 +236,7 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, Error **errp)
+static void pnv_core_realize_child(Object *child, XICSState *xics, Error
**errp)
{
Error *local_err = NULL;
CPUState *cs = CPU(child);
@@ -244,7 +248,7 @@ static void pnv_core_realize_child(Object *child, Error
**errp)
return;
}
- powernv_cpu_init(cpu, &local_err);
+ powernv_cpu_init(cpu, xics, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -291,7 +295,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
for (j = 0; j < cc->nr_threads; j++) {
obj = pc->threads + j * size;
- pnv_core_realize_child(obj, &local_err);
+ pnv_core_realize_child(obj, &pnv->xics, &local_err);
if (local_err) {
goto err;
}
--
2.7.4
- [Qemu-ppc] [PATCH v6 00/10] ppc/pnv: reworking the interrupt controller, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 01/10] ppc/xics: introduce a helper to insert a new ics, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 02/10] ppc/xics: add a xics_get_cpu_index_by_pir helper, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 03/10] ppc/xics: add a 'realize' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 04/10] ppc/xics: add a 'set_nr_servers' handler to the xics_common class, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 05/10] ppc/pnv: add a XICS object to the PowerNV machine, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 06/10] ppc/pnv: add MMIO regions for ICPs, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 07/10] ppc/pnv: link the CPUs to the machine XICS,
Cédric Le Goater <=
- [Qemu-ppc] [PATCH v6 08/10] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 09/10] ppc/pnv: Add OCC model stub with interrupt support, Cédric Le Goater, 2016/11/08
- [Qemu-ppc] [PATCH v6 10/10] ppc/pnv: Add Naples chip support for LPC interrupts, Cédric Le Goater, 2016/11/08