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[Qemu-ppc] [PULL 09/19] target-ppc: Implement bcdctn. instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 09/19] target-ppc: Implement bcdctn. instruction |
Date: |
Tue, 15 Nov 2016 13:48:54 +1100 |
From: Jose Ricardo Ziviani <address@hidden>
bcdctn. converts from BCD to National numeric format. National format
uses a byte to represent a digit where the most significant nibble is
always 0x3 and the least sign. nibbles is the digit itself.
Signed-off-by: Jose Ricardo Ziviani <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 43 +++++++++++++++++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 4 ++++
3 files changed, 48 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5e88e4e..180c5d0 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -379,6 +379,7 @@ DEF_HELPER_4(vpermxor, void, avr, avr, avr, avr)
DEF_HELPER_4(bcdadd, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsub, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
+DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index c79d3ec..d4106a9 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2578,6 +2578,15 @@ static uint16_t get_national_digit(ppc_avr_t *reg, int n)
#endif
}
+static void set_national_digit(ppc_avr_t *reg, uint8_t val, int n)
+{
+#if defined(HOST_WORDS_BIGENDIAN)
+ reg->u16[8 - n] = val;
+#else
+ reg->u16[n] = val;
+#endif
+}
+
static int bcd_cmp_mag(ppc_avr_t *a, ppc_avr_t *b)
{
int i;
@@ -2744,6 +2753,40 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b,
uint32_t ps)
return cr;
}
+uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int cr = 0;
+ int sgnb = bcd_get_sgn(b);
+ int invalid = (sgnb == 0);
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+ int ox_flag = (b->u64[HI_IDX] != 0) || ((b->u64[LO_IDX] >> 32) != 0);
+
+ for (i = 1; i < 8; i++) {
+ set_national_digit(&ret, 0x30 + bcd_get_digit(b, i, &invalid), i);
+
+ if (unlikely(invalid)) {
+ break;
+ }
+ }
+ set_national_digit(&ret, (sgnb == -1) ? NATIONAL_NEG : NATIONAL_PLUS, 0);
+
+ cr = bcd_cmp_zero(b);
+
+ if (ox_flag) {
+ cr |= 1 << CRF_SO;
+ }
+
+ if (unlikely(invalid)) {
+ cr = 1 << CRF_SO;
+ }
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index 90448e9..795e55c 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -986,10 +986,14 @@ static void gen_##op(DisasContext *ctx) \
GEN_BCD(bcdadd)
GEN_BCD(bcdsub)
GEN_BCD2(bcdcfn)
+GEN_BCD2(bcdctn)
static void gen_xpnd04_1(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 5:
+ gen_bcdctn(ctx);
+ break;
case 7:
gen_bcdcfn(ctx);
break;
--
2.7.4
- [Qemu-ppc] [PULL 01/19] bitops: fix rol/ror when shift is zero, (continued)
- [Qemu-ppc] [PULL 01/19] bitops: fix rol/ror when shift is zero, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 03/19] target-ppc: add vrldnm and vrlwnm instructions, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 16/19] ppc/pnv: fix xscom address translation for POWER9, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 13/19] FU exceptions should carry a cause (IC), David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 14/19] spapr-vty: Fix bad assert() statement, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 06/19] ppc/pnv: fix compile breakage on old gcc, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 11/19] target-ppc: Implement bcdctz. instruction, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 07/19] ppc: Remove some stub POWER6 models, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 02/19] target-ppc: add vrldnmi and vrlwmi instructions, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 05/19] powernv: CPU compatibility modes don't make sense for powernv, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 09/19] target-ppc: Implement bcdctn. instruction,
David Gibson <=
- [Qemu-ppc] [PULL 18/19] tests: add XSCOM tests for the PowerNV machine, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 04/19] target-ppc: add vprtyb[w/d/q] instructions, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 17/19] ppc/pnv: Fix fatal bug on 32-bit hosts, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 12/19] spapr: Fix migration of PCI host bridges from qemu-2.7, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 19/19] boot-serial-test: Add a test for the powernv machine, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 15/19] ppc/pnv: add a 'xscom_core_base' field to PnvChipClass, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 08/19] target-ppc: Implement bcdcfn. instruction, David Gibson, 2016/11/14
- [Qemu-ppc] [PULL 10/19] target-ppc: Implement bcdcfz. instruction, David Gibson, 2016/11/14
- Re: [Qemu-ppc] [Qemu-devel] [PULL 00/19] ppc-for-2.8 queue 20161115, Stefan Hajnoczi, 2016/11/15