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Re: [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instruction
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions |
Date: |
Thu, 24 Nov 2016 13:52:53 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 11/24/2016 06:53 AM, Nikunj A Dadhania wrote:
>> David Gibson <address@hidden> writes:
>>
>>> [ Unknown signature status ]
>>> On Wed, Nov 23, 2016 at 05:07:18PM +0530, Nikunj A Dadhania wrote:
>>>> From: Avinesh Kumar <address@hidden>
>>>>
>>>> vextublx: Vector Extract Unsigned Byte Left
>>>> vextuhlx: Vector Extract Unsigned Halfword Left
>>>> vextuwlx: Vector Extract Unsigned Word Left
>>>>
>>>> Signed-off-by: Avinesh Kumar <address@hidden>
>>>> Signed-off-by: Nikunj A Dadhania <address@hidden>
>>>
>>> So, when I suggested doing these without helpers before, I had
>>> forgotten that the non-byte versions can straddle the word boundary.
>>> Given that the offset is in a register, not the instruction that does
>>> make it complicated.
>>>
>>> But, this version also relies on working 128-bit arithmetic, AFAICT
>>> this will just fail to build if CONFIG_INT128 isn't defined.
>>
>> It has both the implementation, just that the defines might have
>> confused you:
>>
>> #if defined(HOST_WORDS_BIGENDIAN)
>>
>> # if defined(CONFIG_INT128)
>> # else
>> # endif
>>
>> #else /* !defined (HOST_WORDS_BIGENDIAN) */
>>
>> # if defined(CONFIG_INT128)
>> # else
>> # endif
>>
>> #endif
>
> In include/qemu/int128.h, we do have int128_rshift. So you don't *really*
> have
> to do this by hand, exactly.
Sure, let me add int128_extract as well. Will be helpful.
Regards
Nikunj
- [Qemu-ppc] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions, (continued)
- [Qemu-ppc] [PATCH v1 04/10] target-ppc: Add xscmpexp[dp, qp] instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 03/10] target-ppc: Fix xscmpodp and xscmpudp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 06/10] target-ppc: implement lxsd and lxssp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 07/10] target-ppc: implement stxsd and stxssp, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 05/10] target-ppc: Add xscmpoqp and xscmpuqp instructions, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 08/10] target-ppc: implement lxv/lxvx and stxv/stxvx, Nikunj A Dadhania, 2016/11/23
- [Qemu-ppc] [PATCH v1 09/10] target-ppc: add vextu[bhw]lx instructions, Nikunj A Dadhania, 2016/11/23
[Qemu-ppc] [PATCH v1 10/10] target-ppc: add vextu[bhw]rx instructions, Nikunj A Dadhania, 2016/11/23
Re: [Qemu-ppc] [PATCH v1 ppc-for-2.9 00/10] POWER9 TCG enablements - part8, David Gibson, 2016/11/23