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[Qemu-ppc] [PULL 020/107] target-ppc: move ppc_vsr_t to common header
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 020/107] target-ppc: move ppc_vsr_t to common header |
Date: |
Thu, 2 Feb 2017 16:13:18 +1100 |
From: Nikunj A Dadhania <address@hidden>
The structure and corresponding defines and functions need to be used
outside of fpu_helper.c as well.
Add u8, u16, u32 and Int128 to the structure.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 37 -------------------------------------
target/ppc/internal.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 37 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 696f537..3b867cf 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1777,43 +1777,6 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1,
uint64_t op2)
return helper_efdtsteq(env, op1, op2);
}
-typedef union _ppc_vsr_t {
- uint64_t u64[2];
- uint32_t u32[4];
- float32 f32[4];
- float64 f64[2];
-} ppc_vsr_t;
-
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VsrW(i) u32[i]
-#define VsrD(i) u64[i]
-#else
-#define VsrW(i) u32[3-(i)]
-#define VsrD(i) u64[1-(i)]
-#endif
-
-static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
-{
- if (n < 32) {
- vsr->VsrD(0) = env->fpr[n];
- vsr->VsrD(1) = env->vsr[n];
- } else {
- vsr->u64[0] = env->avr[n-32].u64[0];
- vsr->u64[1] = env->avr[n-32].u64[1];
- }
-}
-
-static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
-{
- if (n < 32) {
- env->fpr[n] = vsr->VsrD(0);
- env->vsr[n] = vsr->VsrD(1);
- } else {
- env->avr[n-32].u64[0] = vsr->u64[0];
- env->avr[n-32].u64[1] = vsr->u64[1];
- }
-}
-
#define float64_to_float64(x, env) x
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index e83ea45..66cde46 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -199,4 +199,46 @@ EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
+typedef union _ppc_vsr_t {
+ uint8_t u8[16];
+ uint16_t u16[8];
+ uint32_t u32[4];
+ uint64_t u64[2];
+ float32 f32[4];
+ float64 f64[2];
+ Int128 s128;
+} ppc_vsr_t;
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define VsrB(i) u8[i]
+#define VsrW(i) u32[i]
+#define VsrD(i) u64[i]
+#else
+#define VsrB(i) u8[15 - (i)]
+#define VsrW(i) u32[3 - (i)]
+#define VsrD(i) u64[1 - (i)]
+#endif
+
+static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+ if (n < 32) {
+ vsr->VsrD(0) = env->fpr[n];
+ vsr->VsrD(1) = env->vsr[n];
+ } else {
+ vsr->u64[0] = env->avr[n - 32].u64[0];
+ vsr->u64[1] = env->avr[n - 32].u64[1];
+ }
+}
+
+static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+ if (n < 32) {
+ env->fpr[n] = vsr->VsrD(0);
+ env->vsr[n] = vsr->VsrD(1);
+ } else {
+ env->avr[n - 32].u64[0] = vsr->u64[0];
+ env->avr[n - 32].u64[1] = vsr->u64[1];
+ }
+}
+
#endif /* PPC_INTERNAL_H */
--
2.9.3
- [Qemu-ppc] [PULL 000/107] ppc-for-2.9 queue 20170202, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 004/107] target-ppc: Fix xscmpodp and xscmpudp instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 007/107] target-ppc: implement lxsd and lxssp instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 001/107] disas/ppc: Fix indefinite articles in comments, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 003/107] target-ppc: rename CRF_* defines as CRF_*_BIT, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 011/107] target-ppc: Implement bcdctsq. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 002/107] target-ppc: Consolidate instruction decode helpers, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 010/107] target-ppc: Implement bcdcfsq. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 006/107] target-ppc: Add xscmpoqp and xscmpuqp instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 008/107] target-ppc: implement stxsd and stxssp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 020/107] target-ppc: move ppc_vsr_t to common header,
David Gibson <=
- [Qemu-ppc] [PULL 014/107] target-ppc: add vextu[bhw][lr]x instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 005/107] target-ppc: Add xscmpexp[dp, qp] instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 021/107] target-ppc: implement stop instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 016/107] pseries: Make cpu_update during CAS unconditional, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 018/107] ppc: Rename cpu_version to compat_pvr, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 013/107] target-ppc: Implement bcdsetsgn. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 024/107] target-ppc: implement xsnegqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 022/107] target-ppc: implement xsabsqp/xsnabsqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 012/107] target-ppc: Implement bcdcpsgn. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 036/107] ppc: Validate compatibility modes when setting, David Gibson, 2017/02/02