[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 027/107] target-ppc: implement lxvl instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 027/107] target-ppc: implement lxvl instruction |
Date: |
Thu, 2 Feb 2017 16:13:25 +1100 |
From: Nikunj A Dadhania <address@hidden>
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes results in:
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/helper.h | 3 +++
target/ppc/mem_helper.c | 35 +++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 3 +++
4 files changed, 70 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3257820..1c70815 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -312,6 +312,9 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
+#if defined(TARGET_PPC64)
+DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 1ab8a6e..c4ddc5b 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -24,6 +24,7 @@
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
+#include "internal.h"
//#define DEBUG_OP
@@ -284,6 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#ifdef TARGET_PPC64
+#define GET_NB(rb) ((rb >> 56) & 0xFF)
+
+#define VSX_LXVL(name, lj) \
+void helper_##name(CPUPPCState *env, target_ulong addr, \
+ target_ulong xt_num, target_ulong rb) \
+{ \
+ int i; \
+ ppc_vsr_t xt; \
+ uint64_t nb = GET_NB(rb); \
+ \
+ xt.s128 = int128_zero(); \
+ if (nb) { \
+ nb = (nb >= 16) ? 16 : nb; \
+ if (msr_le && !lj) { \
+ for (i = 16; i > 16 - nb; i--) { \
+ xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } else { \
+ for (i = 0; i < nb; i++) { \
+ xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } \
+ } \
+ putVSR(xt_num, &xt, env); \
+}
+
+VSX_LXVL(lxvl, 0)
+#undef VSX_LXVL
+#undef GET_NB
+#endif /* TARGET_PPC64 */
+
#undef HI_IDX
#undef LO_IDX
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 7000035..1f64fb7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -240,6 +240,35 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+#ifdef TARGET_PPC64
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA, xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(xt); \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+#endif
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index f684066..62a0afc 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -10,6 +10,9 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE,
PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.9.3
- [Qemu-ppc] [PULL 018/107] ppc: Rename cpu_version to compat_pvr, (continued)
- [Qemu-ppc] [PULL 018/107] ppc: Rename cpu_version to compat_pvr, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 013/107] target-ppc: Implement bcdsetsgn. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 024/107] target-ppc: implement xsnegqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 022/107] target-ppc: implement xsabsqp/xsnabsqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 012/107] target-ppc: Implement bcdcpsgn. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 036/107] ppc: Validate compatibility modes when setting, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 009/107] target-ppc: implement lxv/lxvx and stxv/stxvx, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 019/107] ppc/spapr: implement H_SIGNAL_SYS_RESET, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 025/107] target-ppc: implement xscpsgnqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 033/107] pseries: Add pseries-2.9 machine type, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 027/107] target-ppc: implement lxvl instruction,
David Gibson <=
- [Qemu-ppc] [PULL 017/107] ppc: Clean up and QOMify hypercall emulation, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 015/107] pseries: Always use core objects for CPU construction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 037/107] qtest: add netfilter tests for ppc64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 023/107] target-ppc: Implement bcd_is_valid function, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 045/107] hw/ppc: QOM'ify spapr_vio.c, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 038/107] qtest: add display-vga-test to ppc64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 032/107] prep: do not use global variable to access nvram, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 031/107] hw/ppc/spapr: Fix boot path of usb-host storage devices, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 039/107] libqos: fix spapr qpci_map(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 044/107] hw/ppc: QOM'ify ppce500_spin.c, David Gibson, 2017/02/02