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[Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift val
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation |
Date: |
Thu, 2 Feb 2017 16:14:43 +1100 |
From: Suraj Jitindar Singh <address@hidden>
We are calculating the authority mask register key value wrong.
The pte entry contains the key value with the two upper bits and the three
lower bits stored separately. We should use these two portions to get a 5
bit value, not or them together which will only give us a 3 bit value.
Fix this.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu-hash64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index ab5d347..7a0b7fc 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -85,7 +85,7 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
#define HPTE64_R_C 0x0000000000000080ULL
#define HPTE64_R_R 0x0000000000000100ULL
#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
-#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \
+#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
(((x) & HPTE64_R_KEY_LO) >> 9))
#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
--
2.9.3
- Re: [Qemu-ppc] [Qemu-devel] [PULL 050/107] prep: add IBM RS/6000 7020 (40p) machine emulation, (continued)
- [Qemu-ppc] [PULL 065/107] target-ppc: Add xscvqpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 064/107] target-ppc: Add xscvdpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 055/107] target-ppc: Use correct precision for FPRF setting, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 073/107] ppc: Implement bcdus. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 096/107] target/ppc: Remove unused POWERPC_FAMILY(POWER), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 072/107] ppc: Implement bcds. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 097/107] target/ppc/cpu-models: Fix/remove bad CPU aliases, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 093/107] target/ppc: Add pcr_supported to POWER9 cpu class definition, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 098/107] ppc: switch to constants within BUILD_BUG_ON, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation,
David Gibson <=
- [Qemu-ppc] [PULL 107/107] hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 103/107] tcg/POWER9: NOOP the cp_abort instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02