[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction |
Date: |
Thu, 2 Feb 2017 16:14:17 +1100 |
From: Nikunj A Dadhania <address@hidden>
xvxexpsp: VSX Vector Extract Exponent Single Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 17 +++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 18 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index b66272e..160a80c 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1396,6 +1396,23 @@ static void gen_xviexpdp(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+static void gen_xvxexpsp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
+ TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
+ TCGv_i64 xbh = cpu_vsrh(xB(ctx->opcode));
+ TCGv_i64 xbl = cpu_vsrl(xB(ctx->opcode));
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(xth, xbh, 23);
+ tcg_gen_andi_i64(xth, xth, 0xFF000000FF);
+ tcg_gen_shri_i64(xtl, xbl, 23);
+ tcg_gen_andi_i64(xtl, xtl, 0xFF000000FF);
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 253a5c4..eb7334a 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -126,6 +126,7 @@ GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
+GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, (continued)
- [Qemu-ppc] [PULL 105/107] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 107/107] hw/ppc/pnv: Use error_report instead of hw_error if a ROM file can't be found, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 057/107] target-ppc: Add xsxexpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 103/107] tcg/POWER9: NOOP the cp_abort instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 060/107] pxb: Restrict to x86, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 075/107] target-ppc: Add xsiexpdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 062/107] ppc: Add ppc_set_compat_all(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction,
David Gibson <=
- [Qemu-ppc] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 092/107] powerpc/cpu-models: rename ISAv3.00 logical PVR definition, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 091/107] target-ppc: Add xvcv[hpsp, sphp] instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 071/107] host-utils: Implement unsigned quadword left/right shift and unit tests, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 076/107] target-ppc: Add xsiexpqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 083/107] target-ppc: Add xscvqps[d, w]z instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 104/107] target/ppc/mmu_hash64: Fix printing unsigned as signed int, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 088/107] target-ppc: Add xscvsdqp and xscvudqp instructions, David Gibson, 2017/02/02