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[Qemu-ppc] [PULL 076/107] target-ppc: Add xsiexpqp instruction
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 076/107] target-ppc: Add xsiexpqp instruction |
Date: |
Thu, 2 Feb 2017 16:14:14 +1100 |
From: Nikunj A Dadhania <address@hidden>
xsiexpqp: VSX Scalar Insert Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate/vsx-impl.inc.c | 22 ++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 23 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 2d09225..ed392aa 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1263,6 +1263,28 @@ static void gen_xsiexpdp(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+static void gen_xsiexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+ TCGv_i64 xah = cpu_vsrh(rA(ctx->opcode) + 32);
+ TCGv_i64 xal = cpu_vsrl(rA(ctx->opcode) + 32);
+ TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32);
+ TCGv_i64 t0;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(xth, xah, 0x8000FFFFFFFFFFFF);
+ tcg_gen_andi_i64(t0, xbh, 0x7FFF);
+ tcg_gen_shli_i64(t0, t0, 48);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_mov_i64(xtl, xal);
+ tcg_temp_free_i64(t0);
+}
+
static void gen_xsxsigdp(DisasContext *ctx)
{
TCGv rt = cpu_gpr[rD(ctx->opcode)];
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index 5980ac6..09b91c3 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -121,6 +121,7 @@ GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02,
0x00000001),
GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
GEN_HANDLER_E(xsiexpdp, 0x3C, 0x16, 0x1C, 0, PPC_NONE, PPC2_ISA300),
+GEN_VSX_XFORM_300(xsiexpqp, 0x4, 0x1B, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, (continued)
- [Qemu-ppc] [PULL 099/107] target-ppc: Add MMU model check for booke machines, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 094/107] ppc: Remove unused function cpu_ppc601_rtc_init(), David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 087/107] target-ppc: Use ppc_vsr_t.f128 in xscmp[o, u, exp]qp, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 079/107] target-ppc: Add xvxexpsp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 053/107] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 074/107] ppc: Implement bcdsr. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 092/107] powerpc/cpu-models: rename ISAv3.00 logical PVR definition, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 091/107] target-ppc: Add xvcv[hpsp, sphp] instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 082/107] target-ppc: Add xvxsigdp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 071/107] host-utils: Implement unsigned quadword left/right shift and unit tests, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 076/107] target-ppc: Add xsiexpqp instruction,
David Gibson <=
- [Qemu-ppc] [PULL 083/107] target-ppc: Add xscvqps[d, w]z instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 104/107] target/ppc/mmu_hash64: Fix printing unsigned as signed int, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 088/107] target-ppc: Add xscvsdqp and xscvudqp instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 102/107] target/ppc/debug: Print LPCR register value if register exists, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 077/107] target-ppc: Add xviexpsp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 090/107] target-ppc: Add xsmulqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 100/107] target-ppc: Add xvtstdc[sp, dp] instructions, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 086/107] ppc: Implement bcdutrunc. instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 089/107] target-ppc: Add xsdivqp instruction, David Gibson, 2017/02/02
- [Qemu-ppc] [PULL 080/107] target-ppc: Add xvxexpdp instruction, David Gibson, 2017/02/02