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[Qemu-ppc] [PATCH 6/6] target-ppc: add mcrxrx instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH 6/6] target-ppc: add mcrxrx instruction |
Date: |
Thu, 9 Feb 2017 16:04:05 +0530 |
mcrxrx: Move to CR from XER Extended
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 724ad17..72c8a46 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3761,6 +3761,29 @@ static void gen_mcrxr(DisasContext *ctx)
tcg_gen_movi_tl(cpu_ca, 0);
}
+#ifdef TARGET_PPC64
+/* mcrxrx */
+static void gen_mcrxrx(DisasContext *ctx)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
+
+ /* copy OV and OV32 */
+ tcg_gen_trunc_tl_i32(t0, cpu_so);
+ tcg_gen_shli_i32(dst, t0, 1);
+ tcg_gen_or_i32(dst, dst, t0);
+ tcg_gen_shli_i32(dst, dst, 2);
+ /* copy CA and CA32 */
+ tcg_gen_trunc_tl_i32(t0, cpu_ca);
+ tcg_gen_shli_i32(t1, t0, 1);
+ tcg_gen_or_i32(t1, t1, t0);
+ tcg_gen_or_i32(dst, dst, t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+}
+#endif
+
/* mfcr mfocrf */
static void gen_mfcr(DisasContext *ctx)
{
@@ -6430,6 +6453,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801,
PPC_MISC),
#if defined(TARGET_PPC64)
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
--
2.7.4
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, (continued)
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/09
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/09
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/12
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/13
- Re: [Qemu-ppc] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Richard Henderson, 2017/02/13
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/16
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Richard Henderson, 2017/02/16
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/16
- Re: [Qemu-ppc] [Qemu-devel] [PATCH 5/6] target-ppc: support for 32-bit carry and overflow, Richard Henderson, 2017/02/17
[Qemu-ppc] [PATCH 6/6] target-ppc: add mcrxrx instruction,
Nikunj A Dadhania <=
Re: [Qemu-ppc] [PATCH 0/6] POWER9 TCG enablements - part15, David Gibson, 2017/02/09