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[Qemu-ppc] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all ins
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv |
Date: |
Mon, 20 Feb 2017 15:04:32 +1100 |
The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
---
target/ppc/mmu-hash64.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 24d9901..7c5d589 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -640,7 +640,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState
*env,
if (msr_ir) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HISI;
@@ -658,7 +666,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState
*env, uint64_t dar,
if (msr_dr) {
vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
} else {
- vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ switch (env->mmu_model) {
+ case POWERPC_MMU_3_00:
+ /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+ vpm = true;
+ break;
+ default:
+ vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+ break;
+ }
}
if (vpm && !msr_hv) {
cs->exception_index = POWERPC_EXCP_HDSI;
--
2.5.5
- Re: [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition, (continued)
[Qemu-ppc] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define, Suraj Jitindar Singh, 2017/02/19
[Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/02/19
Re: [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9, David Gibson, 2017/02/22
[Qemu-ppc] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv,
Suraj Jitindar Singh <=
[Qemu-ppc] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/02/19
[Qemu-ppc] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/02/19
[Qemu-ppc] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/02/19
[Qemu-ppc] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/02/19