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[Qemu-ppc] [PATCH v1 00/10] POWER9 TCG enablements - part15
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v1 00/10] POWER9 TCG enablements - part15 |
Date: |
Mon, 20 Feb 2017 15:41:51 +0530 |
This series contains implentation of CA32 and OV32 bits added to the
ISA 3.0. Various fixed-point arithmetic instructions are updated to take
care of the newer flags.
Finally the last patch adds new instruction mcrxrx, that helps reading
the carry (CA and CA32) and the overflow (OV and OV32) flags
Nikunj A Dadhania (10):
target/ppc: support for 32-bit carry and overflow
target/ppc: Update ca32 in arithmetic add
target/ppc: move subf logic block
target/ppc: compute ca32 for arithmetic substract
target/ppc: update overflow flags for add/sub
target/ppc: use tcg ops for neg instruction
target/ppc: update ov/ov32 for nego
target/ppc: add ov32 flag for multiply low insns
target/ppc: add ov32 flag in divide operations
target/ppc: add mcrxrx instruction
target/ppc/cpu.h | 30 +++++++++++
target/ppc/int_helper.c | 49 ++++++------------
target/ppc/translate.c | 134 +++++++++++++++++++++++++++++++++++++++---------
3 files changed, 155 insertions(+), 58 deletions(-)
--
2.7.4
- [Qemu-ppc] [PATCH v1 00/10] POWER9 TCG enablements - part15,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v1 06/10] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/20
- [Qemu-ppc] [PATCH v1 03/10] target/ppc: move subf logic block, Nikunj A Dadhania, 2017/02/20
- [Qemu-ppc] [PATCH v1 08/10] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/20
- [Qemu-ppc] [PATCH v1 10/10] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/20
- [Qemu-ppc] [PATCH v1 01/10] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/20