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[Qemu-ppc] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instruct
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions |
Date: |
Wed, 22 Feb 2017 17:33:31 +1100 |
From: Bharata B Rao <address@hidden>
xscvqpudz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Doubleword format
xscvqpuwz: VSX Scalar truncate & Convert Quad-Precision format to
Unsigned Word format
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/fpu_helper.c | 2 ++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 96f9801..58aee64 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3086,6 +3086,8 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64,
f128, VsrD(0), \
VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
0xffffffff80000000ULL)
+VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
+VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
/* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
* op - instruction mnemonic
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 007a837..6d77661 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -442,6 +442,8 @@ DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvqpdp, void, env, i32)
DEF_HELPER_2(xscvqpsdz, void, env, i32)
DEF_HELPER_2(xscvqpswz, void, env, i32)
+DEF_HELPER_2(xscvqpudz, void, env, i32)
+DEF_HELPER_2(xscvqpuwz, void, env, i32)
DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvsdqp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c
b/target/ppc/translate/vsx-impl.inc.c
index 8de8cd0..7f12908 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -819,6 +819,8 @@ GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0,
PPC2_VSX207)
GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpsdz, 0x04, 0x1A, 0x19, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvqpswz, 0x04, 0x1A, 0x09, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscvqpudz, 0x04, 0x1A, 0x11, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscvqpuwz, 0x04, 0x1A, 0x01, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvsdqp, 0x04, 0x1A, 0x0A, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c
b/target/ppc/translate/vsx-ops.inc.c
index e20ca32..5030c4a 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -131,6 +131,8 @@ GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16,
0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpuwz, 0x04, 0x1A, 0x01, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
--
2.9.3
- [Qemu-ppc] [PULL 07/43] ppc: implement xssubqp instruction, (continued)
- [Qemu-ppc] [PULL 07/43] ppc: implement xssubqp instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 02/43] spapr: move spapr_core_[foo]plug() callbacks close to machine code in spapr.c, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 05/43] ppc: implement xsrqpxp instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 01/43] spapr: cpu core: separate child threads destruction from machine state operations, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 13/43] target-ppc: implement store atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 15/43] target-ppc: add slbieg instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 14/43] target-ppc: generate exception for copy/paste, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions,
David Gibson <=
- [Qemu-ppc] [PULL 17/43] target-ppc: add wait instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 04/43] ppc: implement xsrqpi[x] instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 12/43] target-ppc: implement load atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 20/43] ppc4xx: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag, David Gibson, 2017/02/22