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[Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode |
Date: |
Wed, 22 Feb 2017 17:33:27 +1100 |
From: Bharata B Rao <address@hidden>
Power ISA 3.0 introduces a few quadruple precision floating point
instructions that support round-to-odd rounding mode. The
round-to-odd mode is explained as under:
Let Z be the intermediate arithmetic result or the operand of a convert
operation. If Z can be represented exactly in the target format, the
result is Z. Otherwise the result is either Z1 or Z2 whichever is odd.
Here Z1 and Z2 are the next larger and smaller numbers representable
in the target format respectively.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
fpu/softfloat.c | 21 ++++++++++++++++++++-
include/fpu/softfloat.h | 2 ++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index c295f31..5ccba76 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -623,6 +623,9 @@ static float64 roundAndPackFloat64(flag zSign, int zExp,
uint64_t zSig,
case float_round_down:
roundIncrement = zSign ? 0x3ff : 0;
break;
+ case float_round_to_odd:
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ break;
default:
abort();
}
@@ -632,8 +635,10 @@ static float64 roundAndPackFloat64(flag zSign, int zExp,
uint64_t zSig,
|| ( ( zExp == 0x7FD )
&& ( (int64_t) ( zSig + roundIncrement ) < 0 ) )
) {
+ bool overflow_to_inf = roundingMode != float_round_to_odd &&
+ roundIncrement != 0;
float_raise(float_flag_overflow | float_flag_inexact, status);
- return packFloat64( zSign, 0x7FF, - ( roundIncrement == 0 ));
+ return packFloat64(zSign, 0x7FF, -(!overflow_to_inf));
}
if ( zExp < 0 ) {
if (status->flush_to_zero) {
@@ -651,6 +656,13 @@ static float64 roundAndPackFloat64(flag zSign, int zExp,
uint64_t zSig,
if (isTiny && roundBits) {
float_raise(float_flag_underflow, status);
}
+ if (roundingMode == float_round_to_odd) {
+ /*
+ * For round-to-odd case, the roundIncrement depends on
+ * zSig which just changed.
+ */
+ roundIncrement = (zSig & 0x400) ? 0 : 0x3ff;
+ }
}
}
if (roundBits) {
@@ -1149,6 +1161,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t
zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}
@@ -1168,6 +1183,7 @@ static float128 roundAndPackFloat128(flag zSign, int32_t
zExp,
if ( ( roundingMode == float_round_to_zero )
|| ( zSign && ( roundingMode == float_round_up ) )
|| ( ! zSign && ( roundingMode == float_round_down ) )
+ || (roundingMode == float_round_to_odd)
) {
return
packFloat128(
@@ -1215,6 +1231,9 @@ static float128 roundAndPackFloat128(flag zSign, int32_t
zExp,
case float_round_down:
increment = zSign && zSig2;
break;
+ case float_round_to_odd:
+ increment = !(zSig1 & 0x1) && zSig2;
+ break;
default:
abort();
}
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 842ec6b..8a39028 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -180,6 +180,8 @@ enum {
float_round_up = 2,
float_round_to_zero = 3,
float_round_ties_away = 4,
+ /* Not an IEEE rounding mode: round to the closest odd mantissa value */
+ float_round_to_odd = 5,
};
/*----------------------------------------------------------------------------
--
2.9.3
- [Qemu-ppc] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow, (continued)
- [Qemu-ppc] [PULL 03/43] spapr: make cpu core unplug follow expected hotunplug call flow, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 11/43] spapr: fix off-by-one error in spapr_ovec_populate_dt(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 13/43] target-ppc: implement store atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 15/43] target-ppc: add slbieg instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 23/43] softfloat: Add float128_to_uint64_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 14/43] target-ppc: generate exception for copy/paste, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 26/43] target-ppc: Add xscvqpudz and xscvqpuwz instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 17/43] target-ppc: add wait instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 09/43] target-ppc: Add xsmaxcdp and xsmincdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 04/43] ppc: implement xsrqpi[x] instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 22/43] softfloat: Add round-to-odd rounding mode,
David Gibson <=
- [Qemu-ppc] [PULL 12/43] target-ppc: implement load atomic instruction, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 20/43] ppc4xx: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 27/43] target/ppc: Fix LPCR DPFD mask define, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 31/43] hw/pci-host/prep: Do not use hw_error() in realize function, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 35/43] pc: pass apic_id to pc_find_cpu_slot() directly so lookup could be done without CPU object, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 39/43] machine: replace query_hotpluggable_cpus() callback with has_hotpluggable_cpus flag, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 24/43] softfloat: Add float128_to_uint32_round_to_zero(), David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 19/43] mac99: replace debug printf with trace points, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 10/43] target-ppc: Add xsmaxjdp and xsminjdp instructions, David Gibson, 2017/02/22
- [Qemu-ppc] [PULL 30/43] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, David Gibson, 2017/02/22