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Re: [Qemu-ppc] [PATCH v3 06/10] target/ppc: update overflow flags for ad
From: |
Nikunj A Dadhania |
Subject: |
Re: [Qemu-ppc] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub |
Date: |
Thu, 23 Feb 2017 10:16:20 +0530 |
User-agent: |
Notmuch/0.21 (https://notmuchmail.org) Emacs/25.0.94.1 (x86_64-redhat-linux-gnu) |
Richard Henderson <address@hidden> writes:
> On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
>> * SO and OV reflects overflow of the 64-bit result in 64-bit mode and
>> overflow of the low-order 32-bit result in 32-bit mode
>>
>> * OV32 reflects overflow of the low-order 32-bit independent of the mode
>>
>> Signed-off-by: Nikunj A Dadhania <address@hidden>
>> ---
>> target/ppc/translate.c | 15 ++++++++++++---
>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index f3f92aa..43366e7 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -809,10 +809,19 @@ static inline void
>> gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
>> tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
>> }
>> tcg_temp_free(t0);
>> - if (NARROW_MODE(ctx)) {
>> - tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>> + if (is_isa300(ctx)) {
>> + tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
>> + if (NARROW_MODE(ctx)) {
>> + tcg_gen_mov_tl(cpu_ov, cpu_ov32);
>> + } else {
>> + tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
>> + }
>> + } else {
>> + if (NARROW_MODE(ctx)) {
>> + tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
>> + }
>> + tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>> }
>> - tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
>
> We're computing this two different ways for no reason. How about
>
> if (NARROW_MODE(ctx)) {
> tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
> if (is_isa300(ctx)) {
> tcg_gen_mov_tl(cpu_ov32, cpu_ov);
> }
> } else {
> if (is_isa300(ctx)) {
> tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
> }
> tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
> }
Yes, no need to extend-sign and shift. Will incorparate.
Regards
Nikunj
- Re: [Qemu-ppc] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow, (continued)
[Qemu-ppc] [PATCH v3 02/10] target/ppc: optimize gen_write_xer(), Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 04/10] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 09/10] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 08/10] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 07/10] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
[Qemu-ppc] [PATCH v3 10/10] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/22
Re: [Qemu-ppc] [PATCH v3 00/10] POWER9 TCG enablements - part15, David Gibson, 2017/02/22