[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [QEMU-PPC] [PATCH V4 00/11] target/ppc: Implement POWER9 pser
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [QEMU-PPC] [PATCH V4 00/11] target/ppc: Implement POWER9 pseries tcg legacy support |
Date: |
Fri, 24 Feb 2017 12:05:06 +1100 |
This is V4 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.
To use a POWER9 cpu provide the command line option "-cpu POWER9".
This series attempts to avoid precluding KVM-HV support for the POWER9
cpu model but doesn't attempt to support KVM-PR or the powernv machine
for the POWER9 cpu model as these aren't currently supported or
implemented and further code changes will be required in the event these
are implemented.
This series is based on the hpt-cleanup branch.
The changes from V3 are as follows:
- Add a flag POWERPC_MMU_V3 to mmu_model and check this where appropriate
- Add LPCR_HR define
- Remove function ppc_hash64_set_sdr1() and split this into new patch
- Add file mmu-book3s-v3.c to handle new ISAV3 generic mmu code
- Rebase on hpt-cleanup branch
Suraj Jitindar Singh (11):
target/ppc/POWER9: Add ISAv3.00 MMU definition
target/ppc: Fix LPCR DPFD mask define
target/ppc/POWER9: Adapt LPCR handling for POWER9
target/ppc/POWER9: Direct all instr and data storage interrupts to the
hypv
target/ppc: Add patb_entry to sPAPRMachineState
target/ppc: Remove the function ppc_hash64_set_sdr1()
target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
target/ppc/POWER9: Add POWER9 mmu fault handler
target/ppc/POWER9: Add POWER9 pa-features definition
target/ppc/POWER9: Add cpu_has_work function for POWER9
hw/ppc/spapr: Add POWER9 to pseries cpu models
hw/ppc/spapr.c | 47 ++++++
hw/ppc/spapr_cpu_core.c | 3 +
include/hw/ppc/spapr.h | 1 +
target/ppc/Makefile.objs | 2 +-
target/ppc/cpu-qom.h | 7 +-
target/ppc/cpu.h | 23 ++-
target/ppc/mmu-book3s-v3.c | 37 +++++
target/ppc/mmu-book3s-v3.h | 50 ++++++
target/ppc/mmu-hash64.c | 48 +++---
target/ppc/mmu-hash64.h | 3 -
target/ppc/mmu_helper.c | 33 +++-
target/ppc/translate.c | 7 +-
target/ppc/translate_init.c | 389 +++++++++++++++++++++++++++++---------------
13 files changed, 488 insertions(+), 162 deletions(-)
create mode 100644 target/ppc/mmu-book3s-v3.c
create mode 100644 target/ppc/mmu-book3s-v3.h
--
2.5.5
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 00/11] target/ppc: Implement POWER9 pseries tcg legacy support,
Suraj Jitindar Singh <=
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 01/11] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 02/11] target/ppc: Fix LPCR DPFD mask define, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 03/11] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 04/11] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/02/23