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[Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPA
From: |
Suraj Jitindar Singh |
Subject: |
[Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPAPRMachineState |
Date: |
Fri, 24 Feb 2017 12:05:11 +1100 |
ISA v3.00 adds the idea of a partition table which is used to store the
address translation details for all partitions on the system. The partition
table consists of double word entries indexed by partition id where the second
double word contains the location of the process table in guest memory. The
process table is registered by the guest via a h-call.
We need somewhere to store the address of the process table so we add an entry
to the sPAPRMachineState struct called patb_entry to represent the second
doubleword of a single partition table entry corresponding to the current
guest. We need to store this value so we know if the guest is using radix or
hash translation and the location of the corresponding process table in guest
memory. Since we only have a single guest per qemu instance, we only need one
entry.
Since the partition table is technically a hypervisor resource we require that
access to it is abstracted by the virtual hypervisor through the get_patbe()
call. Currently the value of the entry is never set (and thus
defaults to 0 indicating hash), but it will be required to both implement
POWER9 kvm support and tcg radix support.
We also add this field to be migrated as part of the sPAPRMachineState as we
will need it on the receiving side as the guest will never tell us this
information again and we need it to perform translation.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
---
V2 -> V3:
- Only add patbe to migration stream if non-zero
V3 -> V4:
- Remove reference to set_patbe() in commit message
---
hw/ppc/spapr.c | 29 +++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 1 +
target/ppc/cpu.h | 1 +
3 files changed, 31 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c159961..b60b4f5 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1018,6 +1018,13 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp,
}
}
+static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
+{
+ sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
+
+ return spapr->patb_entry;
+}
+
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) &
HPTE64_V_HPTE_DIRTY)
@@ -1195,6 +1202,8 @@ static void ppc_spapr_reset(void)
/* Check for unknown sysbus devices */
foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
+ spapr->patb_entry = 0;
+
/* Allocate and/or reset the hash page table */
spapr_reallocate_hpt(spapr,
spapr_hpt_shift_for_ramsize(machine->maxram_size),
@@ -1381,6 +1390,24 @@ static const VMStateDescription vmstate_spapr_ov5_cas = {
},
};
+static bool spapr_patb_entry_needed(void *opaque)
+{
+ sPAPRMachineState *spapr = opaque;
+
+ return !!spapr->patb_entry;
+}
+
+static const VMStateDescription vmstate_spapr_patb_entry = {
+ .name = "spapr_patb_entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = spapr_patb_entry_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(patb_entry, sPAPRMachineState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
static const VMStateDescription vmstate_spapr = {
.name = "spapr",
.version_id = 3,
@@ -1398,6 +1425,7 @@ static const VMStateDescription vmstate_spapr = {
},
.subsections = (const VMStateDescription*[]) {
&vmstate_spapr_ov5_cas,
+ &vmstate_spapr_patb_entry,
NULL
}
};
@@ -2968,6 +2996,7 @@ static void spapr_machine_class_init(ObjectClass *oc,
void *data)
vhc->map_hptes = spapr_map_hptes;
vhc->unmap_hptes = spapr_unmap_hptes;
vhc->store_hpte = spapr_store_hpte;
+ vhc->get_patbe = spapr_get_patbe;
}
static const TypeInfo spapr_machine_info = {
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index f9b17d8..2975967 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -63,6 +63,7 @@ struct sPAPRMachineState {
void *htab;
uint32_t htab_shift;
+ uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
hwaddr rma_size;
int vrma_adjust;
ssize_t rtas_size;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 09ee374..c720fc0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1219,6 +1219,7 @@ struct PPCVirtualHypervisorClass {
hwaddr ptex, int n);
void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
uint64_t pte0, uint64_t pte1);
+ uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
};
#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
--
2.5.5
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 00/11] target/ppc: Implement POWER9 pseries tcg legacy support, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 01/11] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 02/11] target/ppc: Fix LPCR DPFD mask define, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 03/11] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 04/11] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPAPRMachineState,
Suraj Jitindar Singh <=
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 06/11] target/ppc: Remove the function ppc_hash64_set_sdr1(), Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 08/11] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 07/11] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/02/23