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[Qemu-ppc] [PATCH v5 4/8] target/ppc: update overflow flags for add/sub
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v5 4/8] target/ppc: update overflow flags for add/sub |
Date: |
Fri, 24 Feb 2017 11:16:40 +0530 |
* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
overflow of the low-order 32-bit result in 32-bit mode
* OV32 reflects overflow of the low-order 32-bit independent of the mode
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e083082..16f422f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -810,9 +810,16 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
}
tcg_temp_free(t0);
if (NARROW_MODE(ctx)) {
- tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
+ tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, cpu_ov);
+ }
+ } else {
+ if (is_isa300(ctx)) {
+ tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
+ }
+ tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
}
- tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
--
2.7.4
- [Qemu-ppc] [PATCH v5 0/8] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 2/8] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 1/8] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 3/8] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 4/8] target/ppc: update overflow flags for add/sub,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v5 6/8] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 8/8] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 5/8] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/24
- [Qemu-ppc] [PATCH v5 7/8] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/24