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[Qemu-ppc] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low ins
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns |
Date: |
Mon, 27 Feb 2017 10:27:59 +0530 |
For Multiply Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Multiply DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d4d9941..ccf3bff 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1285,6 +1285,9 @@ static void gen_mullwo(DisasContext *ctx)
tcg_gen_sari_i32(t0, t0, 31);
tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
tcg_gen_extu_i32_tl(cpu_ov, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, cpu_ov);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
tcg_temp_free_i32(t0);
@@ -1346,6 +1349,9 @@ static void gen_mulldo(DisasContext *ctx)
tcg_gen_sari_i64(t0, t0, 63);
tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, cpu_ov);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
tcg_temp_free_i64(t0);
--
2.7.4
- [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 3/8] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v6 8/8] target/ppc: add mcrxrx instruction, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 1/8] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 5/8] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 7/8] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 4/8] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 2/8] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/26
- Re: [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15, David Gibson, 2017/02/27