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[Qemu-ppc] [PATCH v6 8/8] target/ppc: add mcrxrx instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [PATCH v6 8/8] target/ppc: add mcrxrx instruction |
Date: |
Mon, 27 Feb 2017 10:28:01 +0530 |
mcrxrx: Move to CR from XER Extended
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 982e66f..6e6868b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3819,6 +3819,28 @@ static void gen_mcrxr(DisasContext *ctx)
tcg_gen_movi_tl(cpu_ca, 0);
}
+#ifdef TARGET_PPC64
+/* mcrxrx */
+static void gen_mcrxrx(DisasContext *ctx)
+{
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
+
+ /* copy OV and OV32 */
+ tcg_gen_shli_tl(t0, cpu_ov, 1);
+ tcg_gen_or_tl(t0, t0, cpu_ov32);
+ tcg_gen_shli_tl(t0, t0, 2);
+ /* copy CA and CA32 */
+ tcg_gen_shli_tl(t1, cpu_ca, 1);
+ tcg_gen_or_tl(t1, t1, cpu_ca32);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_trunc_tl_i32(dst, t0);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+#endif
+
/* mfcr mfocrf */
static void gen_mfcr(DisasContext *ctx)
{
@@ -6488,6 +6510,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801,
PPC_MISC),
#if defined(TARGET_PPC64)
GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
--
2.7.4
- [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 3/8] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 6/8] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 8/8] target/ppc: add mcrxrx instruction,
Nikunj A Dadhania <=
- [Qemu-ppc] [PATCH v6 1/8] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 5/8] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 7/8] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 4/8] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/26
- [Qemu-ppc] [PATCH v6 2/8] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/26
- Re: [Qemu-ppc] [PATCH v6 0/8] POWER9 TCG enablements - part15, David Gibson, 2017/02/27