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Re: [Qemu-ppc] [QEMU-PPC] [PATCH V4 07/11] target/ppc: Don't gen an SDR1
From: |
Suraj Jitindar Singh |
Subject: |
Re: [Qemu-ppc] [QEMU-PPC] [PATCH V4 07/11] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation |
Date: |
Mon, 27 Feb 2017 16:42:47 +1100 |
On Mon, 2017-02-27 at 15:06 +1100, Balbir Singh wrote:
> On Fri, Feb 24, 2017 at 12:05:13PM +1100, Suraj Jitindar Singh wrote:
> >
> > POWER9 doesn't have a storage description register 1 (SDR1) which
> > is used
> > to store the base and size of the hash table. Thus we don't need to
> > generate this register on the POWER9 cpu model. While we're here,
> > the
> > register generation code for 970, POWER5+, POWER<7/8/9> in general
> > is a
> > mess where we call a generic function from a model specific
> > function which
> > then attempts to call model specific functions, so rework this for
> > readability.
> >
> > We update ppc_cpu_dump_state so that "info registers" will only
> > display
> > the value of sdr1 if the register has been generated.
> >
> > As mentioned above the register generation for the pcc->init_proc
> > function for 970, POWER5+, POWER7, POWER8 and POWER9 has been
> > reworked
> > for improved clarity. Instead of calling init_proc_book3s_64 which
> > then
> > attempts to generate the correct registers through a mess of if
> > statements,
> > we remove this function and instead call the appropriate register
> > generation functions directly. This follows the register generation
> > model
> > used for earlier cpu models (pre-970) whereby cpu specific
> > registers are
> > generated directly in the init_proc function and makes it easier to
> > add/remove specific registers for new cpu models.
> >
> Honestly I prefer less code duplication and I don't think the parsing
> of
> the generation based on model numbers is complex. The problem with
> duplication
> is it almost always leads to BUGS
I guess the advantage of duplicating it is hopefully no-one will ever
touch the register generation for old processors, and thus can't break
it. While when it's all in the same function inevitibly someone will
make a change and break an old processor which we never test.
>
> Balbir Singh.
- Re: [Qemu-ppc] [QEMU-PPC] [PATCH V4 05/11] target/ppc: Add patb_entry to sPAPRMachineState, (continued)
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 06/11] target/ppc: Remove the function ppc_hash64_set_sdr1(), Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 08/11] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 07/11] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 09/11] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 10/11] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/02/23
- [Qemu-ppc] [QEMU-PPC] [PATCH V4 11/11] hw/ppc/spapr: Add POWER9 to pseries cpu models, Suraj Jitindar Singh, 2017/02/23