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[Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract |
Date: |
Wed, 1 Mar 2017 15:43:33 +1100 |
From: Nikunj A Dadhania <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eba83ef..e083082 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -827,7 +827,11 @@ static inline void gen_op_arith_compute_ca32(DisasContext
*ctx,
}
t0 = tcg_temp_new();
- tcg_gen_xor_tl(t0, arg0, arg1);
+ if (sub) {
+ tcg_gen_eqv_tl(t0, arg0, arg1);
+ } else {
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ }
tcg_gen_xor_tl(t0, t0, res);
tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
tcg_temp_free(t0);
@@ -1378,17 +1382,22 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ca32, cpu_ca);
+ }
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
zero = tcg_const_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
+ gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, 0);
tcg_temp_free(zero);
tcg_temp_free(inv1);
} else {
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
tcg_gen_sub_tl(t0, arg2, arg1);
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, 1);
}
} else if (add_ca) {
/* Since we're ignoring carry-out, we can simplify the
--
2.9.3
- [Qemu-ppc] [PULL 00/50] ppc-for-2.9 queue 20170301, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 01/50] target/ppc: move cpu_[read, write]_xer to cpu.c, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 05/50] target/ppc: introduce helper_update_ov_legacy, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 02/50] target/ppc: optimize gen_write_xer(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 06/50] sysemu: support up to 1024 vCPUs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract,
David Gibson <=
- [Qemu-ppc] [PULL 09/50] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 14/50] target/ppc: Remove the function ppc_hash64_set_sdr1(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 20/50] target/ppc: use tcg ops for neg instruction, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 04/50] spapr: generate DT node names, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 16/50] target/ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 15/50] target/ppc: Correct SDR1 masking, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 07/50] target/ppc: Fix KVM-HV HPTE accessors, David Gibson, 2017/02/28