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[Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub |
Date: |
Wed, 1 Mar 2017 15:43:34 +1100 |
From: Nikunj A Dadhania <address@hidden>
* SO and OV reflects overflow of the 64-bit result in 64-bit mode and
overflow of the low-order 32-bit result in 32-bit mode
* OV32 reflects overflow of the low-order 32-bit independent of the mode
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e083082..16f422f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -810,9 +810,16 @@ static inline void gen_op_arith_compute_ov(DisasContext
*ctx, TCGv arg0,
}
tcg_temp_free(t0);
if (NARROW_MODE(ctx)) {
- tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
+ tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, cpu_ov);
+ }
+ } else {
+ if (is_isa300(ctx)) {
+ tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1);
+ }
+ tcg_gen_extract_tl(cpu_ov, cpu_ov, 63, 1);
}
- tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
--
2.9.3
- [Qemu-ppc] [PULL 00/50] ppc-for-2.9 queue 20170301, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 01/50] target/ppc: move cpu_[read, write]_xer to cpu.c, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 05/50] target/ppc: introduce helper_update_ov_legacy, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 02/50] target/ppc: optimize gen_write_xer(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 06/50] sysemu: support up to 1024 vCPUs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 09/50] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub,
David Gibson <=
- [Qemu-ppc] [PULL 14/50] target/ppc: Remove the function ppc_hash64_set_sdr1(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 20/50] target/ppc: use tcg ops for neg instruction, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 04/50] spapr: generate DT node names, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 16/50] target/ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 15/50] target/ppc: Correct SDR1 masking, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 07/50] target/ppc: Fix KVM-HV HPTE accessors, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 34/50] ppc/xics: remove xics_find_source(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 24/50] spapr/pci: populate PCI DT in reverse order, David Gibson, 2017/02/28