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[Qemu-ppc] [PULL 22/50] target/ppc: add ov32 flag in divide operations
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 22/50] target/ppc: add ov32 flag in divide operations |
Date: |
Wed, 1 Mar 2017 15:43:37 +1100 |
From: Nikunj A Dadhania <address@hidden>
Add helper_div_compute_ov() in the int_helper for updating the overflow
flags.
For Divide Word:
SO, OV, and OV32 bits reflects overflow of the 32-bit result
For Divide DoubleWord:
SO, OV, and OV32 bits reflects overflow of the 64-bit result
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ccf3bff..982e66f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1021,6 +1021,9 @@ static inline void gen_op_arith_divw(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
if (compute_ov) {
tcg_gen_extu_i32_tl(cpu_ov, t2);
+ if (is_isa300(ctx)) {
+ tcg_gen_extu_i32_tl(cpu_ov32, t2);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
tcg_temp_free_i32(t0);
@@ -1092,6 +1095,9 @@ static inline void gen_op_arith_divd(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
if (compute_ov) {
tcg_gen_mov_tl(cpu_ov, t2);
+ if (is_isa300(ctx)) {
+ tcg_gen_mov_tl(cpu_ov32, t2);
+ }
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
tcg_temp_free_i64(t0);
@@ -1110,10 +1116,10 @@ static void glue(gen_, name)(DisasContext *ctx)
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
sign, compute_ov); \
}
-/* divwu divwu. divwuo divwuo. */
+/* divdu divdu. divduo divduo. */
GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
-/* divw divw. divwo divwo. */
+/* divd divd. divdo divdo. */
GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
--
2.9.3
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, (continued)
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 20/50] target/ppc: use tcg ops for neg instruction, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 04/50] spapr: generate DT node names, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 16/50] target/ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 15/50] target/ppc: Correct SDR1 masking, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 07/50] target/ppc: Fix KVM-HV HPTE accessors, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 34/50] ppc/xics: remove xics_find_source(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 24/50] spapr/pci: populate PCI DT in reverse order, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 33/50] ppc/xics: use the QOM interface to resend irqs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 22/50] target/ppc: add ov32 flag in divide operations,
David Gibson <=
- [Qemu-ppc] [PULL 42/50] ppc/xics: simplify spapr_dt_xics() interface, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 47/50] ppc/xics: move ics-simple post_load under the machine, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 27/50] ppc/xics: remove set_nr_servers() handler from XICSStateClass, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 49/50] ppc/xics: rename 'ICPState *' variables to 'icp', David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 21/50] target/ppc: add ov32 flag for multiply low insns, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 39/50] ppc/xics: simplify the cpu_setup() handler, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 08/50] pseries: Minor cleanups to HPT management hypercalls, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 12/50] target/ppc: Eliminate htab_base and htab_mask variables, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 43/50] ppc/xics: register the reset handler of ICP objects, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 37/50] ppc/xics: extend the QOM interface to handle ICPs, David Gibson, 2017/02/28