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Re: [Qemu-ppc] [PATCH v4 6/8] spapr: move spapr_populate_pa_features()
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH v4 6/8] spapr: move spapr_populate_pa_features() |
Date: |
Fri, 17 Mar 2017 14:01:29 +1100 |
User-agent: |
Mutt/1.8.0 (2017-02-23) |
On Thu, Mar 16, 2017 at 05:08:18PM +1100, Sam Bobroff wrote:
> In the next patch, spapr_fixup_cpu_dt() will need to call
> spapr_populate_pa_features() so move it's definition up without making
> any other changes.
>
> Signed-off-by: Sam Bobroff <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> hw/ppc/spapr.c | 122
> ++++++++++++++++++++++++++++-----------------------------
> 1 file changed, 61 insertions(+), 61 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 8f14914eea..bcdedd3618 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -227,6 +227,67 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int
> offset, CPUState *cs)
> return ret;
> }
>
> +/* Populate the "ibm,pa-features" property */
> +static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int
> offset)
> +{
> + uint8_t pa_features_206[] = { 6, 0,
> + 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> + uint8_t pa_features_207[] = { 24, 0,
> + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
> + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
> + /* Currently we don't advertise any of the "new" ISAv3.00 functionality
> */
> + uint8_t pa_features_300[] = { 64, 0,
> + 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
> + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
> + 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
> +
> + uint8_t *pa_features;
> + size_t pa_size;
> +
> + switch (POWERPC_MMU_VER(env->mmu_model)) {
> + case POWERPC_MMU_VER_2_06:
> + pa_features = pa_features_206;
> + pa_size = sizeof(pa_features_206);
> + break;
> + case POWERPC_MMU_VER_2_07:
> + pa_features = pa_features_207;
> + pa_size = sizeof(pa_features_207);
> + break;
> + case POWERPC_MMU_VER_3_00:
> + pa_features = pa_features_300;
> + pa_size = sizeof(pa_features_300);
> + break;
> + default:
> + return;
> + }
> +
> + if (env->ci_large_pages) {
> + /*
> + * Note: we keep CI large pages off by default because a 64K capable
> + * guest provisioned with large pages might otherwise try to map a
> qemu
> + * framebuffer (or other kind of memory mapped PCI BAR) using 64K
> pages
> + * even if that qemu runs on a 4k host.
> + * We dd this bit back here if we are confident this is not an issue
> + */
> + pa_features[3] |= 0x20;
> + }
> + if (kvmppc_has_cap_htm() && pa_size > 24) {
> + pa_features[24] |= 0x80; /* Transactional memory support */
> + }
> +
> + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features,
> pa_size)));
> +}
> +
> static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
> {
> int ret = 0, offset, cpus_offset;
> @@ -379,67 +440,6 @@ static int spapr_populate_memory(sPAPRMachineState
> *spapr, void *fdt)
> return 0;
> }
>
> -/* Populate the "ibm,pa-features" property */
> -static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int
> offset)
> -{
> - uint8_t pa_features_206[] = { 6, 0,
> - 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
> - uint8_t pa_features_207[] = { 24, 0,
> - 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
> - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
> - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
> - 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
> - /* Currently we don't advertise any of the "new" ISAv3.00 functionality
> */
> - uint8_t pa_features_300[] = { 64, 0,
> - 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
> - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> - 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
> - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
> - 0x00, 0x00, 0x00, 0x00 }; /* 60 - 63 */
> -
> - uint8_t *pa_features;
> - size_t pa_size;
> -
> - switch (POWERPC_MMU_VER(env->mmu_model)) {
> - case POWERPC_MMU_VER_2_06:
> - pa_features = pa_features_206;
> - pa_size = sizeof(pa_features_206);
> - break;
> - case POWERPC_MMU_VER_2_07:
> - pa_features = pa_features_207;
> - pa_size = sizeof(pa_features_207);
> - break;
> - case POWERPC_MMU_VER_3_00:
> - pa_features = pa_features_300;
> - pa_size = sizeof(pa_features_300);
> - break;
> - default:
> - return;
> - }
> -
> - if (env->ci_large_pages) {
> - /*
> - * Note: we keep CI large pages off by default because a 64K capable
> - * guest provisioned with large pages might otherwise try to map a
> qemu
> - * framebuffer (or other kind of memory mapped PCI BAR) using 64K
> pages
> - * even if that qemu runs on a 4k host.
> - * We dd this bit back here if we are confident this is not an issue
> - */
> - pa_features[3] |= 0x20;
> - }
> - if (kvmppc_has_cap_htm() && pa_size > 24) {
> - pa_features[24] |= 0x80; /* Transactional memory support */
> - }
> -
> - _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features,
> pa_size)));
> -}
> -
> static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
> sPAPRMachineState *spapr)
> {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [PATCH v4 4/8] target/ppc: Add new H-CALL shells for in memory table translation, (continued)
- [Qemu-ppc] [PATCH v4 4/8] target/ppc: Add new H-CALL shells for in memory table translation, Sam Bobroff, 2017/03/16
- [Qemu-ppc] [PATCH v4 3/8] spapr: Only setup HPT if necessary, Sam Bobroff, 2017/03/16
- [Qemu-ppc] [PATCH v4 1/8] spapr: Add ibm, processor-radix-AP-encodings to the device tree, Sam Bobroff, 2017/03/16
- [Qemu-ppc] [PATCH v4 8/8] spapr: Workaround for broken radix guests, Sam Bobroff, 2017/03/16
- [Qemu-ppc] [PATCH v4 6/8] spapr: move spapr_populate_pa_features(), Sam Bobroff, 2017/03/16
- Re: [Qemu-ppc] [PATCH v4 6/8] spapr: move spapr_populate_pa_features(),
David Gibson <=
- [Qemu-ppc] [PATCH v4 7/8] spapr: Enable ISA 3.0 MMU mode selection via CAS, Sam Bobroff, 2017/03/16
- [Qemu-ppc] [PATCH v4 5/8] target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL, Sam Bobroff, 2017/03/16
- Re: [Qemu-ppc] [PATCH v4 0/8] ISA 3.00 KVM guest support, David Gibson, 2017/03/17