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[Qemu-ppc] [PULL 04/22] target/ppc: Generate fence operations
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 04/22] target/ppc: Generate fence operations |
Date: |
Wed, 10 May 2017 17:00:57 +1000 |
From: Nikunj A Dadhania <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4d..4a1f24a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2971,6 +2971,7 @@ static void gen_stswx(DisasContext *ctx)
/* eieio */
static void gen_eieio(DisasContext *ctx)
{
+ tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
}
#if !defined(CONFIG_USER_ONLY)
@@ -3008,6 +3009,7 @@ static void gen_isync(DisasContext *ctx)
if (!ctx->pr) {
gen_check_tlb_flush(ctx, false);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_stop_exception(ctx);
}
@@ -3028,6 +3030,7 @@ static void gen_##name(DisasContext *ctx)
\
tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
tcg_gen_mov_tl(cpu_reserve, t0); \
tcg_gen_mov_tl(cpu_reserve_val, gpr); \
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
tcg_temp_free(t0); \
}
@@ -3177,6 +3180,10 @@ static void gen_conditional_store(DisasContext *ctx,
TCGv EA,
tcg_gen_br(l2);
gen_set_label(l1);
+
+ /* Address mismatch implies failure. But we still need to provide the
+ memory barrier semantics of the instruction. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
gen_set_label(l2);
@@ -3308,6 +3315,7 @@ static void gen_sync(DisasContext *ctx)
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
}
/* wait */
--
2.9.3
- [Qemu-ppc] [PULL 00/22] ppc-for-2.10 queue 20170510, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 05/22] cpus: Fix CPU unplug for MTTCG, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 04/22] target/ppc: Generate fence operations,
David Gibson <=
- [Qemu-ppc] [PULL 08/22] ppc/xics: Fix stale irq->status bits after get, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 03/22] cputlb: handle first atomic write to the page, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 07/22] target/ppc: do not reset reserve_addr in exec_enter, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 06/22] tcg: enable MTTCG by default for PPC64 on x86, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built as submodule, David Gibson, 2017/05/10
- [Qemu-ppc] [PULL 19/22] ppc: xics: fix compilation with CentOS 6, David Gibson, 2017/05/10