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[Qemu-ppc] [PULL 07/17] target-ppc: Fix openpic timer read register offs
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 07/17] target-ppc: Fix openpic timer read register offset |
Date: |
Tue, 6 Jun 2017 12:51:25 +1000 |
From: Aaron Larson <address@hidden>
openpic_tmr_read() is incorrectly computing register offset of the
TCCR, TBCR, TVPR, and TDR registers when accessing the open pic timer
registers. Specifically the offset of timer registers for
openpic_tmr_read() is not accounting for the timer frequency reporting
register (TFFR) which is the first register in the "tmr" memory
region.
openpic_tmr_write() *is* correctly computing the offset by adding
0x10f0 to the address prior to computing the register index. This
patch instead subtracts 0x10 in both the read and write routines and
eliminates some other gratuitous differences between the functions.
Signed-off-by: Aaron Larson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/openpic.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 4349e45..f966d06 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -796,27 +796,24 @@ static uint64_t openpic_gbl_read(void *opaque, hwaddr
addr, unsigned len)
}
static void openpic_tmr_write(void *opaque, hwaddr addr, uint64_t val,
- unsigned len)
+ unsigned len)
{
OpenPICState *opp = opaque;
int idx;
- addr += 0x10f0;
-
DPRINTF("%s: addr %#" HWADDR_PRIx " <= %08" PRIx64 "\n",
- __func__, addr, val);
+ __func__, (addr + 0x10f0), val);
if (addr & 0xF) {
return;
}
- if (addr == 0x10f0) {
+ if (addr == 0) {
/* TFRR */
opp->tfrr = val;
return;
}
-
+ addr -= 0x10; /* correct for TFRR */
idx = (addr >> 6) & 0x3;
- addr = addr & 0x30;
switch (addr & 0x30) {
case 0x00: /* TCCR */
@@ -844,16 +841,17 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr
addr, unsigned len)
uint32_t retval = -1;
int idx;
- DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr);
+ DPRINTF("%s: addr %#" HWADDR_PRIx "\n", __func__, addr + 0x10f0);
if (addr & 0xF) {
goto out;
}
- idx = (addr >> 6) & 0x3;
- if (addr == 0x0) {
+ if (addr == 0) {
/* TFRR */
retval = opp->tfrr;
goto out;
}
+ addr -= 0x10; /* correct for TFRR */
+ idx = (addr >> 6) & 0x3;
switch (addr & 0x30) {
case 0x00: /* TCCR */
retval = opp->timers[idx].tccr;
@@ -861,10 +859,10 @@ static uint64_t openpic_tmr_read(void *opaque, hwaddr
addr, unsigned len)
case 0x10: /* TBCR */
retval = opp->timers[idx].tbcr;
break;
- case 0x20: /* TIPV */
+ case 0x20: /* TVPR */
retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
break;
- case 0x30: /* TIDE (TIDR) */
+ case 0x30: /* TDR */
retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
break;
}
--
2.9.4
- [Qemu-ppc] [PULL 00/17] ppc-for-2.10 queue 20170606, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 01/17] migration: remove register_savevm(), David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 07/17] target-ppc: Fix openpic timer read register offset,
David Gibson <=
- [Qemu-ppc] [PULL 12/17] spapr/drc: don't migrate DRC of cold-plugged CPUs and LMBs, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 02/17] migration: Mark CPU states dirty before incoming migration/loadvm, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 10/17] ppc/pnv: check the return value of fdt_setprop(), David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 09/17] spapr_nvram: Check return value from blk_getlength(), David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 04/17] spapr: Abolish DRC get_fdt method, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 17/17] spapr: Remove some non-useful properties on DRC objects, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 05/17] spapr: Abolish DRC set_configured method, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 03/17] spapr: Move DRC RTAS calls into spapr_drc.c, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 08/17] target/ppc: Fixup set_spr error in h_register_process_table, David Gibson, 2017/06/05
- [Qemu-ppc] [PULL 16/17] spapr: Eliminate spapr_drc_get_type_str(), David Gibson, 2017/06/05