[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-ppc] [PATCH 19/25] spapr: add hcalls support for the XIVE inte

From: Benjamin Herrenschmidt
Subject: Re: [Qemu-ppc] [PATCH 19/25] spapr: add hcalls support for the XIVE interrupt mode
Date: Tue, 05 Dec 2017 08:50:26 -0600

On Tue, 2017-12-05 at 18:00 +1100, David Gibson wrote:
> > The CPU revision. But we won't introduce XIVE exploitation mode on 
> > anything else than DD2.0 which has full XIVE support. Even STORE_EOI 
> > that we should be adding.
> Hrm.  Host CPU?  That's a problem - if guest visible properties like
> this vary with the host CPU, migration breaks.

I don't think this is going to be a problem in practice. The
availability of trigger comes from OPAL but in practice, all virtual
interrupts are going to support it always, only some of the HW
originated ones (PCIe MSIs for example and LSIs) won't. And we don't
migrate with PCIe devices passed through.

So the guest need the info, but we should be ok with migration from P9
DD2.0 onwards. Nobody sane cares about P9 DD1.0.

Any future chip will have to ensure that we don't lose that property in
HW least we lost migration, but that would break AIX too so I'm
reasonably confident the HW guys will get that right ;-)

> > 
> > > If it varies with host capabilities, that's going to be real pain for
> > > migration.
> > 
> > Yes. I am not aware of any future extension but I agree this is
> > something we need to keep an eye on.
> I'm not talking about future extension, I'm meaning right now.

No, no issue right now.


reply via email to

[Prev in Thread] Current Thread [Next in Thread]