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[Qemu-ppc] [PULL 07/24] pcc: define the Power-saving mode Exit Cause Ena
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 07/24] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass |
Date: |
Fri, 15 Dec 2017 16:54:18 +1100 |
From: Cédric Le Goater <address@hidden>
and use the value to define precisely the default value of the LPCR in
the helper routine cpu_ppc_set_papr()
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/cpu-qom.h | 1 +
target/ppc/translate_init.c | 23 +++++++++++------------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 429b47f959..deaa46a14b 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -191,6 +191,7 @@ typedef struct PowerPCCPUClass {
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
+ uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
powerpc_input_t bus_model;
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 4e11e6f489..074c3a1d45 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8535,6 +8535,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8704,6 +8705,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
#ifdef CONFIG_SOFTMMU
@@ -8898,11 +8901,13 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#if !defined(CONFIG_USER_ONLY)
void cpu_ppc_set_papr(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
@@ -8932,8 +8937,7 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
PPCVirtualHypervisor *vhyp)
lpcr->default_value &= ~LPCR_RMLS;
lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
- switch (env->mmu_model) {
- case POWERPC_MMU_3_00:
+ if (env->mmu_model == POWERPC_MMU_3_00) {
/* By default we choose legacy mode and switch to new hash or radix
* when a register process table hcall is made. So disable process
* tables and guest translation shootdown by default
@@ -8947,18 +8951,13 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu,
PPCVirtualHypervisor *vhyp)
} else {
lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
}
- lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
- LPCR_OEE;
- break;
- default:
- /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
- * bit 47 and 48 which are reserved on P7. Here we set them all, which
- * will work as expected for both implementations
- */
- lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
+ /* Also set the power-saving mode bits which depend on the CPU
+ * family
+ */
+ lpcr->default_value |= pcc->lpcr_pm;
+
/* We should be followed by a CPU reset but update the active value
* just in case...
*/
--
2.14.3
- [Qemu-ppc] [PULL 02/24] ppc/xics: remove useless if condition, (continued)
- [Qemu-ppc] [PULL 02/24] ppc/xics: remove useless if condition, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 03/24] spapr: Add pseries-2.12 machine type, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 10/24] spapr/rtas: disable the decrementer interrupt when a CPU is unplugged, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 04/24] spapr_cpu_core: instantiate CPUs separately, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 11/24] spapr/rtas: fix reboot of a a SMP TCG guest, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 09/24] e500: fix pci host bridge class/type, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 16/24] spapr: introduce a spapr_irq_set_lsi() helper, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 23/24] spapr: Assume msi_nonbroken, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 12/24] spapr/rtas: do not reset the MSR in stop-self command, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 14/24] ppc/xics: assign of the CPU 'intc' pointer under the core, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 07/24] pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass,
David Gibson <=
- [Qemu-ppc] [PULL 13/24] ppc/xics: introduce an icp_create() helper, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 17/24] spapr: introduce a spapr_qirq() helper, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 18/24] spapr: replace numa_get_node() with lookup in pc-dimm list, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 21/24] target/ppc: introduce the PPC_BIT() macro, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 08/24] openpic: debug w/ info_report(), David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 05/24] e500: name openpic and pci host bridge, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 06/24] nvram: add AT24Cx i2c eeprom, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 24/24] spapr: don't initialize PATB entry if max-cpu-compat < power9, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 19/24] spapr: fix LSI interrupt specifiers in the device tree, David Gibson, 2017/12/15
- [Qemu-ppc] [PULL 20/24] spapr_events: drop bogus cell from "interrupt-ranges" property, David Gibson, 2017/12/15