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Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 em


From: BALATON Zoltan
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH v2 5/8] hw/timer: Add basic M41T80 emulation
Date: Thu, 14 Jun 2018 09:54:41 +0200 (CEST)
User-agent: Alpine 2.21 (BSF 202 2017-01-01)

On Thu, 14 Jun 2018, David Gibson wrote:
On Wed, Jun 13, 2018 at 04:13:57PM +0200, BALATON Zoltan wrote:
I don't see the problem. The addr register selects the register to read or
write. It is set by the first write when the device is accessed the first
time (this is denoted by addr == -1 (or really any negative value). The
device has 20 registers and trying to read any register outside addr between
0-19 will result in returning 0 and logging a warning about invalid register
in m41t80_recv. What could fail here when guest sends garbage? It will set
addr to invalid value and try to read non-exitent register and get an error
just like for any other nonexistent value of addr (or start to read from
register 0 if it manages to set a negative value). All writes of registers
are ignored currently (except setting addr by the first write). What should
be enforced here?

Ah, I see your point.  I mean strictly we should match the hardware
behaviour if you write garbage addresses here, but really I don't
think it matters much.

Problem is like usual I have no idea what the real hardware does. I've only seen the datasheet, never seen real device and have no way to test. All the clients I've tested seem to be OK with the current emulation so unless someone has more info on how this should work I think we can live with this version and then fix it later if found to be needed.

Regards,
BALATON Zoltan



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