[Qemu-ppc] [PATCH 0/6] ppc/pnv: new Pnv8Chip and Pnv9Chip models

[Cédric Le Goater]

Hello,

First are some cleanups around the ISA bus of the machine. Then
additions of new chip models for the different processor the PowerNV
machine supports, which come with their respective "powernv8" and
"powernv9" machines.


For some obscure reasons, this patchset breaks 'make check' :

  TEST: tests/spapr-phb-test... (pid=8196)
  qemu-system-ppc64: -device spapr-pci-host-bridge,index=30: 
spapr-pci-host-bridge needs a pseries machine
  Broken pipe
 FAIL: tests/spapr-phb-test

Any idea ? I guess this is because of the new machines. 

Thanks,

C. 

Cédric Le Goater (6):
  ppc/pnv: introduce a 'primary' field under the LPC model
  ppc/pnv: move the details of the ISA bus creation under the LPC model
  ppc/pnv: introduce an 'isa_bus_name' field under the LPC model
  ppc/pnv: introduce a pnv_chip_core_realize() routine
  ppc/pnv: introduce a new intc_create() operation to the chip model
  ppc/pnv: introduce Pnv8Chip and Pnv9Chip models

 include/hw/ppc/pnv.h     |  29 +++-
 include/hw/ppc/pnv_lpc.h |   6 +-
 hw/ppc/pnv.c             | 380 +++++++++++++++++++++++++++++------------------
 hw/ppc/pnv_core.c        |  18 +--
 hw/ppc/pnv_lpc.c         |  55 +++++--
 5 files changed, 322 insertions(+), 166 deletions(-)

-- 
2.13.6