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[Qemu-ppc] [PATCH 10/13] target/ppc: Use MO_ALIGN for EXIWX and ECOWX
From: |
Richard Henderson |
Subject: |
[Qemu-ppc] [PATCH 10/13] target/ppc: Use MO_ALIGN for EXIWX and ECOWX |
Date: |
Tue, 26 Jun 2018 09:19:18 -0700 |
This avoids the need for gen_check_align entirely.
Signed-off-by: Richard Henderson <address@hidden>
---
target/ppc/translate.c | 25 ++++---------------------
1 file changed, 4 insertions(+), 21 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 53ca8f0114..c2a28be6d7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2388,23 +2388,6 @@ static inline void gen_addr_add(DisasContext *ctx, TCGv
ret, TCGv arg1,
}
}
-static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
-{
- TCGLabel *l1 = gen_new_label();
- TCGv t0 = tcg_temp_new();
- TCGv_i32 t1, t2;
- tcg_gen_andi_tl(t0, EA, mask);
- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
- t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
- t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
- gen_update_nip(ctx, ctx->base.pc_next - 4);
- gen_helper_raise_exception_err(cpu_env, t1, t2);
- tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
- gen_set_label(l1);
- tcg_temp_free(t0);
-}
-
static inline void gen_align_no_le(DisasContext *ctx)
{
gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
@@ -4706,8 +4689,8 @@ static void gen_eciwx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_EXT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x03);
- gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
+ DEF_MEMOP(MO_UL | MO_ALIGN));
tcg_temp_free(t0);
}
@@ -4719,8 +4702,8 @@ static void gen_ecowx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_EXT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- gen_check_align(ctx, t0, 0x03);
- gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
+ tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx,
+ DEF_MEMOP(MO_UL | MO_ALIGN));
tcg_temp_free(t0);
}
--
2.17.1
- Re: [Qemu-ppc] [PATCH 03/13] target/ppc: Use atomic store for STQ, (continued)
- [Qemu-ppc] [PATCH 05/13] target/ppc: Remove POWERPC_EXCP_STCX, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 06/13] target/ppc: Tidy gen_conditional_store, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 07/13] target/ppc: Split out gen_load_locked, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 09/13] target/ppc: Split out gen_st_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 08/13] target/ppc: Split out gen_ld_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 10/13] target/ppc: Use MO_ALIGN for EXIWX and ECOWX,
Richard Henderson <=
- [Qemu-ppc] [PATCH 12/13] target/ppc: Implement the rest of gen_ld_atomic, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 04/13] target/ppc: Use atomic cmpxchg for STQCX, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 11/13] target/ppc: Use atomic min/max helpers, Richard Henderson, 2018/06/26
- [Qemu-ppc] [PATCH 13/13] target/ppc: Implement the rest of gen_st_atomic, Richard Henderson, 2018/06/26
- Re: [Qemu-ppc] [PATCH 00/13] target/ppc improve atomic operations, David Gibson, 2018/06/29