Re: [Qemu-ppc] [PATCH 02/13] target/ppc: Use atomic load for LQ and LQARX

[David Gibson]

On Thu, Jun 28, 2018 at 08:22:38AM -0700, Richard Henderson wrote:
> On 06/27/2018 08:49 PM, David Gibson wrote:
> >> +    /* High part of 128-bit helper return.  */
> >> +    uint64_t retxh;
> >> +
> > 
> > Adding a temporary here is kind of gross.  I guess the helper
> > interface doesn't allow for 128-bit returns, but couldn't you pass a
> > register number into the helper and have it update the right GPR
> > without going through a temp?
> 
> I could pass a pointer, but that would cause ...
> 
> >> +#if defined(TARGET_PPC64) && defined(CONFIG_ATOMIC128)
> >> +DEF_HELPER_FLAGS_3(lq_le_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
> >> +DEF_HELPER_FLAGS_3(lq_be_parallel, TCG_CALL_NO_WG, i64, env, tl, i32)
> 
> ... the helper definitions to lose TCG_CALL_NO_WG, because they *would* write
> to a global register.  Which would cause TCG to discard all of the global 
> guest
> registers cached within host registers.
> 
> I've used this secondary memory return before, in target/s390,
> and to me it seems cleaner than pointers.

Ok, sounds reasonable, applied to ppc-for-3.0.

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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