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[Qemu-ppc] [PULL 25/29] pnv/psi: move the ICSState qemu_irq array under
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 25/29] pnv/psi: move the ICSState qemu_irq array under the PSI device model |
Date: |
Wed, 9 Jan 2019 09:45:56 +1100 |
From: Cédric Le Goater <address@hidden>
Future changes of the ICSState object will remove the qemu_irq array
from under the interrupt controller model. Prepare ground for the PSI
interrupt sources and introduce a new one directly under the PSI
device model.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv_psi.c | 7 ++++---
include/hw/ppc/pnv_psi.h | 1 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 5b969127c3..8ced095063 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -207,7 +207,6 @@ static const uint64_t stat_bits[] = {
void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state)
{
- ICSState *ics = &psi->ics;
uint32_t xivr_reg;
uint32_t stat_reg;
uint32_t src;
@@ -227,14 +226,14 @@ void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool
state)
/* TODO: optimization, check mask here. That means
* re-evaluating when unmasking
*/
- qemu_irq_raise(ics->qirqs[src]);
+ qemu_irq_raise(psi->qirqs[src]);
} else {
psi->regs[stat_reg] &= ~stat_bits[irq];
/* FSP and PSI are muxed so don't lower if either is still set */
if (stat_reg != PSIHB_XSCOM_CR ||
!(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
- qemu_irq_lower(ics->qirqs[src]);
+ qemu_irq_lower(psi->qirqs[src]);
} else {
state = true;
}
@@ -491,6 +490,8 @@ static void pnv_psi_realize(DeviceState *dev, Error **errp)
ics_set_irq_type(ics, i, true);
}
+ psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
+
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index f6af5eae1f..64ac73512e 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -40,6 +40,7 @@ typedef struct PnvPsi {
/* Interrupt generation */
ICSState ics;
+ qemu_irq *qirqs;
/* Registers */
uint64_t regs[PSIHB_XSCOM_MAX];
--
2.20.1
- [Qemu-ppc] [PULL 12/29] target/ppc: move FP and VMX registers into aligned vsr register array, (continued)
- [Qemu-ppc] [PULL 12/29] target/ppc: move FP and VMX registers into aligned vsr register array, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 27/29] ppc/xics: allow ICSState to have an offset 0, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 21/29] ppc/xive: introduce a XiveTCTX pointer under PowerPCCPU, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 19/29] spapr/xive: simplify the sPAPR IRQ qirq method for XIVE, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 20/29] spapr: modify the prototype of the cpu_intc_create() method, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 28/29] spapr: introduce a new sPAPR IRQ backend supporting XIVE and XICS, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 24/29] ppc: export the XICS and XIVE set_irq handlers, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 26/29] spapr: move the qemu_irq array under the machine, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 29/29] spapr: enable XIVE MMIOs at reset, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 22/29] ppc: replace the 'Object *intc' by a 'ICPState *icp' pointer under the CPU, David Gibson, 2019/01/08
- [Qemu-ppc] [PULL 25/29] pnv/psi: move the ICSState qemu_irq array under the PSI device model,
David Gibson <=
- [Qemu-ppc] [PULL 23/29] spapr: return from post_load method when RTC import fails, David Gibson, 2019/01/08
- Re: [Qemu-ppc] [PULL 00/29] ppc-for-4.0 queue 20190109, Peter Maydell, 2019/01/09