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[Qemu-ppc] [PULL 23/50] target/ppc: Add basic support for "new format" H
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 23/50] target/ppc: Add basic support for "new format" HPTE as found on POWER9 |
Date: |
Tue, 26 Feb 2019 15:52:37 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
POWER9 (arch v3) slightly changes the HPTE format. The B bits move
from the first to the second half of the HPTE, and the AVPN/ARPN
are slightly shorter.
However, under SPAPR, the hypercalls still take the old format
(and probably will for the foreseable future).
The simplest way to support this is thus to convert the HPTEs from
new to old format when reading them if the MMU model is v3 and there
is no virtual hypervisor, leaving the rest of the code unchanged.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Moved function to .c since there was no real need for it in the .h]
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/mmu-hash64.c | 17 +++++++++++++++++
target/ppc/mmu-hash64.h | 5 +++++
2 files changed, 22 insertions(+)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index fbefe5b5aa..3c057a8c70 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -490,6 +490,18 @@ static unsigned hpte_page_shift(const
PPCHash64SegmentPageSizes *sps,
return 0; /* Bad page size encoding */
}
+static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1)
+{
+ /* Insert B into pte0 */
+ *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) |
+ ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) <<
+ (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT));
+
+ /* Remove B from pte1 */
+ *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK;
+}
+
+
static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash,
const PPCHash64SegmentPageSizes *sps,
target_ulong ptem,
@@ -515,6 +527,11 @@ static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu,
hwaddr hash,
smp_rmb();
pte1 = ppc_hash64_hpte1(cpu, pteg, i);
+ /* Convert format if necessary */
+ if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) {
+ ppc64_v3_new_to_old_hpte(&pte0, &pte1);
+ }
+
/* This compares V, B, H (secondary) and the AVPN */
if (HPTE64_V_COMPARE(pte0, ptem)) {
*pshift = hpte_page_shift(sps, pte0, pte1);
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index f11efc9cbc..016d6b44ee 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -102,6 +102,11 @@ void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
+/* Format changes for ARCH v3 */
+#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
+#define HPTE64_R_3_0_SSIZE_SHIFT 58
+#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
+
static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
{
if (cpu->vhyp) {
--
2.20.1
- [Qemu-ppc] [PULL 31/50] spapr: Generate FDT fragment for CPUs at configure connector time, (continued)
- [Qemu-ppc] [PULL 31/50] spapr: Generate FDT fragment for CPUs at configure connector time, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 06/50] target/ppc: Add POWER9 exception model, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 12/50] cpus: Properly release the iothread lock when killing a dummy VCPU, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 15/50] tests/device-plug: Add CCW unplug test for s390x, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 17/50] tests/device-plug: Add memory unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 16/50] tests/device-plug: Add CPU core unplug request test for spapr, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 24/50] target/ppc: Fix synchronization of mttcg with broadcast TLB flushes, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 26/50] target/ppc: Rename PATB/PATBE -> PATE, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 14/50] tests/device-plug: Add a simple PCI unplug request test, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 25/50] target/ppc: Flush the TLB locally when the LPIDR is written, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 23/50] target/ppc: Add basic support for "new format" HPTE as found on POWER9,
David Gibson <=
- [Qemu-ppc] [PULL 22/50] target/ppc: Fix ordering of hash MMU accesses, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 28/50] target/ppc: Basic POWER9 bare-metal radix MMU support, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 35/50] spapr: Expose the name of the interrupt controller node, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 27/50] target/ppc: Support for POWER9 native hash, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 30/50] spapr: Generate FDT fragment for LMBs at configure connector time, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 39/50] spapr: populate PHB DRC entries for root DT node, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 46/50] ppc/xive: xive does not have a POWER7 interrupt model, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 29/50] spapr_drc: Allow FDT fragment to be added later, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 33/50] spapr/drc: Drop spapr_drc_attach() fdt argument, David Gibson, 2019/02/25
- [Qemu-ppc] [PULL 38/50] spapr: create DR connectors for PHBs, David Gibson, 2019/02/25