[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PATCH 4/8] target/ppc: introduce avrh_offset() and avrl_offs
From: |
Mark Cave-Ayland |
Subject: |
[Qemu-ppc] [PATCH 4/8] target/ppc: introduce avrh_offset() and avrl_offset() functions |
Date: |
Sun, 3 Mar 2019 17:23:39 +0000 |
These will become more useful later, but initially use this as an aid to
simplify the offset calculation by replacing the HOST_TARGET_BIGENDIAN
sections with the VsrD macro.
Signed-off-by: Mark Cave-Ayland <address@hidden>
---
target/ppc/cpu.h | 10 ++++++++++
target/ppc/translate.c | 24 ++++++++++--------------
2 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d0580c6b6d..326593e0e7 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2603,6 +2603,16 @@ static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env,
int i)
return (uint64_t *)((uintptr_t)env + vsrl_offset(i));
}
+static inline int avrh_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[32 + i].VsrD(0));
+}
+
+static inline int avrl_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[32 + i].VsrD(1));
+}
+
static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
{
return &env->vsr[32 + i];
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 3b1992faf1..f646f359e7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6687,24 +6687,20 @@ static inline void set_fpr(int regno, TCGv_i64 src)
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
{
-#ifdef HOST_WORDS_BIGENDIAN
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 0 :
1)]));
-#else
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 1 :
0)]));
-#endif
+ if (high) {
+ tcg_gen_ld_i64(dst, cpu_env, avrh_offset(regno));
+ } else {
+ tcg_gen_ld_i64(dst, cpu_env, avrl_offset(regno));
+ }
}
static inline void set_avr64(int regno, TCGv_i64 src, bool high)
{
-#ifdef HOST_WORDS_BIGENDIAN
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 0 :
1)]));
-#else
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState,
- vsr[32 + regno].u64[(high ? 1 :
0)]));
-#endif
+ if (high) {
+ tcg_gen_st_i64(src, cpu_env, avrh_offset(regno));
+ } else {
+ tcg_gen_st_i64(src, cpu_env, avrl_offset(regno));
+ }
}
#include "translate/fp-impl.inc.c"
--
2.11.0
[Qemu-ppc] [PATCH 6/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, Mark Cave-Ayland, 2019/03/03
Re: [Qemu-ppc] [PATCH 0/8] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/04