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[Qemu-ppc] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip |
Date: |
Sun, 10 Mar 2019 19:26:50 +1100 |
From: Cédric Le Goater <address@hidden>
The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 18 +++++-------------
include/hw/ppc/pnv.h | 2 ++
2 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 922e3ec48b..6625562d27 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -417,24 +417,12 @@ static int pnv_dt_isa_device(DeviceState *dev, void
*opaque)
return 0;
}
-static int pnv_chip_isa_offset(PnvChip *chip, void *fdt)
-{
- char *name;
- int offset;
-
- name = g_strdup_printf("/address@hidden" PRIx64 "/address@hidden",
- (uint64_t) PNV_XSCOM_BASE(chip),
PNV_XSCOM_LPC_BASE);
- offset = fdt_path_offset(fdt, name);
- g_free(name);
- return offset;
-}
-
/* The default LPC bus of a multichip system is on chip 0. It's
* recognized by the firmware (skiboot) using a "primary" property.
*/
static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
{
- int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt);
+ int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
ForeachPopulateArgs args = {
.fdt = fdt,
.offset = isa_offset,
@@ -866,6 +854,10 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
&error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
+ chip->dt_isa_nodename = g_strdup_printf("/address@hidden" PRIx64
"/address@hidden",
+ (uint64_t) PNV_XSCOM_BASE(chip),
+ PNV_XSCOM_LPC_BASE);
+
/* Interrupt Management Area. This is the memory region holding
* all the Interrupt Control Presenter (ICP) registers */
pnv_chip_icp_realize(chip8, &local_err);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 8d80cb34ee..c81f157f41 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -58,6 +58,8 @@ typedef struct PnvChip {
MemoryRegion xscom_mmio;
MemoryRegion xscom;
AddressSpace xscom_as;
+
+ gchar *dt_isa_nodename;
} PnvChip;
#define TYPE_PNV8_CHIP "pnv8-chip"
--
2.20.1
- [Qemu-ppc] [PULL 42/60] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, (continued)
- [Qemu-ppc] [PULL 42/60] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 50/60] ppc/pnv: add a OCC model class, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 49/60] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 54/60] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 51/60] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip,
David Gibson <=
- [Qemu-ppc] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 44/60] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 55/60] ppc/pnv: add more dummy XSCOM addresses, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 46/60] ppc/pnv: add a LPC Controller class model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 53/60] ppc/pnv: POWER9 XSCOM quad support, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 52/60] ppc/pnv: extend XSCOM core support for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 57/60] target/ppc: add HV support for POWER9, David Gibson, 2019/03/10