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Re: [Qemu-ppc] [Qemu-devel] [PATCH] ppc: Three floating point fixes

From: Aleksandar Markovic
Subject: Re: [Qemu-ppc] [Qemu-devel] [PATCH] ppc: Three floating point fixes
Date: Sun, 18 Aug 2019 22:59:01 +0200

18.08.2019. 10.10, "Richard Henderson" <address@hidden> је написао/ла:
> On 8/16/19 11:59 PM, Aleksandar Markovic wrote:
> >> From: "Paul A. Clarke" <address@hidden>
> ...
> >>   ISA 3.0B has xscvdpspn leaving its result in word 1 of the target
> > register,
> >>   and mffprwz expecting its input to come from word 0 of the source
> > register.
> >>   This sequence fails with QEMU, as a shift is required between those two
> >>   instructions.  However, the hardware splats the result to both word 0
> > and
> >>   word 1 of its output register, so the shift is not necessary.
> >>   Expect a future revision of the ISA to specify this behavior.
> >>
> >
> > Hmmm... Isn't this a gcc bug (using undocumented hardware feature), given
> > everything you said here?
> The key here is "expect a future revision of the ISA to specify this behavior".
> It's clearly within IBM's purview to adjust the specification to document a
> previously undocumented hardware feature.

By no means, yes, the key is in ISA documentation. But, the impression that full original commit message conveys is that the main reason for change is gcc behavior. If we accepted in general that gcc behavior determines QEMU behavior, I am afraid we would be on a very slippery slope - therefore I think the commit message (and possible code comment) should, in my opinion, mention ISA docs as the central reason for change. Paul, is there any tentative release date of the new ISA specification?


> r~

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