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Re: [Qemu-ppc] [PATCH v2 2/2] ppc: Add support for 'mffsce' instruction
From: |
Paul Clarke |
Subject: |
Re: [Qemu-ppc] [PATCH v2 2/2] ppc: Add support for 'mffsce' instruction |
Date: |
Tue, 17 Sep 2019 16:49:56 -0500 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 9/17/19 3:46 PM, Richard Henderson wrote:
> On 9/16/19 1:02 PM, Paul A. Clarke wrote:
>> From: "Paul A. Clarke" <address@hidden>
>>
>> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
>> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
>> This patch adds support for 'mffsce' instruction.
>>
>> 'mffsce' is identical to 'mffs', except that it also clears the exception
>> enable bits in the FPSCR.
>>
>> On CPUs without support for 'mffsce' (below ISA 3.0), the
>> instruction will execute identically to 'mffs'.
>>
>> Signed-off-by: Paul A. Clarke <address@hidden>
>> ---
>> v2: no changes.
>>
>> target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++
>> target/ppc/translate/fp-ops.inc.c | 2 ++
>> 2 files changed, 32 insertions(+)
>
> Didn't I already give a
> Reviewed-by: Richard Henderson <address@hidden>
>
> for this?
You did. Sorry for the confusion. I wasn't sure whether to resend or not,
given the dependence on the other patch and David said he would be waiting for
the respin.
PC