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[PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NV
From: |
David Gibson |
Subject: |
[PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT |
Date: |
Tue, 17 Dec 2019 15:42:41 +1100 |
From: Cédric Le Goater <address@hidden>
When a vCPU is dispatched on a HW thread, its context is pushed in the
thread registers and it is activated by setting the VO bit in the CAM
line word2. The HW grabs the associated NVT, pulls the IPB bits and
merges them with the IPB of the new context. If interrupts were missed
while the vCPU was not dispatched, these are synthesized in this
sequence.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/intc/xive.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7047e45dac..e022bb7afd 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -393,6 +393,57 @@ static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr,
XiveTCTX *tctx,
return qw1w2;
}
+static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
+ uint8_t nvt_blk, uint32_t nvt_idx)
+{
+ XiveNVT nvt;
+ uint8_t ipb;
+
+ /*
+ * Grab the associated NVT to pull the pending bits, and merge
+ * them with the IPB of the thread interrupt context registers
+ */
+ if (xive_router_get_nvt(xrtr, nvt_blk, nvt_idx, &nvt)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVT_W4_IPB, nvt.w4);
+
+ if (ipb) {
+ /* Reset the NVT value */
+ nvt.w4 = xive_set_field32(NVT_W4_IPB, nvt.w4, 0);
+ xive_router_write_nvt(xrtr, nvt_blk, nvt_idx, &nvt, 4);
+
+ /* Merge in current context */
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvt_blk;
+ uint32_t nvt_idx;
+ bool vo;
+
+ xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+ /* First update the registers */
+ xive_tctx_set_os_cam(tctx, qw1w2);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive_tctx_need_resend(XIVE_ROUTER(xptr), tctx, nvt_blk, nvt_idx);
+ }
+}
+
/*
* Define a mapping of "special" operations depending on the TIMA page
* offset and the size of the operation.
@@ -414,6 +465,7 @@ static const XiveTmOp xive_tm_operations[] = {
* effects
*/
{ XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
+ { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx, NULL
},
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL
},
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL },
{ XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll },
--
2.23.0
- [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT, (continued)
- [PULL 30/88] ppc/pnv: Loop on the threads of the chip to find a matching NVT, David Gibson, 2019/12/16
- [PULL 35/88] ppc/pnv: Implement the XiveFabric interface, David Gibson, 2019/12/16
- [PULL 41/88] spapr/xics: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper, David Gibson, 2019/12/16
- [PULL 33/88] ppc/pnv: Fix TIMA indirect access, David Gibson, 2019/12/16
- [PULL 37/88] ppc/xive: Use the XiveFabric and XivePresenter interfaces, David Gibson, 2019/12/16
- [PULL 29/88] ppc/pnv: Instantiate cores separately, David Gibson, 2019/12/16
- [PULL 31/88] ppc: Introduce a ppc_cpu_pir() helper, David Gibson, 2019/12/16
- [PULL 44/88] ppc/xive: Move the TIMA operations to the controller model, David Gibson, 2019/12/16
- [PULL 38/88] ppc/xive: Extend the TIMA operation with a XivePresenter parameter, David Gibson, 2019/12/16
- [PULL 47/88] ppc/xive: Synthesize interrupt from the saved IPB in the NVT,
David Gibson <=
- [PULL 40/88] spapr: Pass the maximum number of vCPUs to the KVM interrupt controller, David Gibson, 2019/12/16
- [PULL 39/88] linux-headers: Update, David Gibson, 2019/12/16
- [PULL 42/88] spapr/xive: Configure number of servers in KVM, David Gibson, 2019/12/16
- [PULL 45/88] ppc/xive: Remove the get_tctx() XiveRouter handler, David Gibson, 2019/12/16
- [PULL 46/88] ppc/xive: Introduce a xive_tctx_ipb_update() helper, David Gibson, 2019/12/16
- [PULL 48/88] ppc/pnv: Introduce a pnv_xive_block_id() helper, David Gibson, 2019/12/16
- [PULL 58/88] ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU models, David Gibson, 2019/12/16
- [PULL 52/88] spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeover, David Gibson, 2019/12/16
- [PULL 57/88] xics: Don't deassert outputs, David Gibson, 2019/12/16
- [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system, David Gibson, 2019/12/16