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[PATCH v5 06/18] target/ppc: Remove RMOR register from POWER9 & POWER10
From: |
David Gibson |
Subject: |
[PATCH v5 06/18] target/ppc: Remove RMOR register from POWER9 & POWER10 |
Date: |
Thu, 20 Feb 2020 14:23:04 +1100 |
Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus
from POWER7 onwards. However the translation mode which the RMOR controls
is no longer supported in POWER9, and so the register has been removed from
the architecture.
Remove it from our model on POWER9 and POWER10.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
---
target/ppc/translate_init.inc.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index ab79975fec..925bc31ca5 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8015,12 +8015,16 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_RMOR, "RMOR",
+ spr_register_hv(env, SPR_HRMOR, "HRMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- spr_register_hv(env, SPR_HRMOR, "HRMOR",
+}
+
+static void gen_spr_rmor(CPUPPCState *env)
+{
+ spr_register_hv(env, SPR_RMOR, "RMOR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -8535,6 +8539,7 @@ static void init_proc_POWER7(CPUPPCState *env)
/* POWER7 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_book3s_purr(env);
gen_spr_power5p_common(env);
@@ -8676,6 +8681,7 @@ static void init_proc_POWER8(CPUPPCState *env)
/* POWER8 Specific Registers */
gen_spr_book3s_ids(env);
+ gen_spr_rmor(env);
gen_spr_amr(env);
gen_spr_iamr(env);
gen_spr_book3s_purr(env);
--
2.24.1
- [PATCH v5 00/18] target/ppc: Correct some errors with real mode handling, David Gibson, 2020/02/19
- [PATCH v5 01/18] ppc: Remove stub support for 32-bit hypervisor mode, David Gibson, 2020/02/19
- [PATCH v5 02/18] ppc: Remove stub of PPC970 HID4 implementation, David Gibson, 2020/02/19
- [PATCH v5 06/18] target/ppc: Remove RMOR register from POWER9 & POWER10,
David Gibson <=
- [PATCH v5 04/18] target/ppc: Introduce ppc_hash64_use_vrma() helper, David Gibson, 2020/02/19
- [PATCH v5 08/18] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS], David Gibson, 2020/02/19
- [PATCH v5 10/18] target/ppc: Only calculate RMLS derived RMA limit on demand, David Gibson, 2020/02/19
- [PATCH v5 05/18] spapr, ppc: Remove VPM0/RMLS hacks for POWER9, David Gibson, 2020/02/19
- [PATCH v5 09/18] target/ppc: Correct RMLS table, David Gibson, 2020/02/19
- [PATCH v5 07/18] target/ppc: Use class fields to simplify LPCR masking, David Gibson, 2020/02/19
- [PATCH v5 12/18] target/ppc: Don't store VRMA SLBE persistently, David Gibson, 2020/02/19
- [PATCH v5 11/18] target/ppc: Streamline construction of VRMA SLB entry, David Gibson, 2020/02/19
- [PATCH v5 16/18] spapr: Don't clamp RMA to 16GiB on new machine types, David Gibson, 2020/02/19
- [PATCH v5 17/18] spapr: Clean up RMA size calculation, David Gibson, 2020/02/19