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Re: [RFC PATCH v2] target/ppc: Enable hardfloat for PPC

From: Peter Maydell
Subject: Re: [RFC PATCH v2] target/ppc: Enable hardfloat for PPC
Date: Fri, 21 Feb 2020 18:26:26 +0000

On Fri, 21 Feb 2020 at 18:04, BALATON Zoltan <address@hidden> wrote:
> On Fri, 21 Feb 2020, Peter Maydell wrote:
> > I think that is the wrong approach. Enabling use of the host
> > FPU should not affect the accuracy of the emulation, which
> > should remain bitwise-correct. We should only be using the
> > host FPU to the extent that we can do that without discarding
> > accuracy. As far as I'm aware that's how the hardfloat support
> > for other guest CPUs that use it works.
> I don't know of a better approach. Please see section 4.2.2 Floating-Point
> Status and Control Register on page 124 in this document:
> https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0
> especially the definition of the FR and FI bits and tell me how can we
> emulate these accurately and use host FPU.

I don't know much about PPC, but if you can't emulate the
guest architecture accurately with the host FPU, then
don't use the host FPU. We used to have a kind of 'hardfloat'
support that was fast but inaccurate, but it was a mess
because it meant that most guest code sort of worked but
some guest code would confusingly misbehave. Deliberately
not correctly emulating the guest CPU/FPU behaviour is not
something I want us to return to.

You're right that sometimes you can't get both speed
and accuracy; other emulators (and especially ones
which are trying to emulate games consoles) may choose
to prefer speed over accuracy. For QEMU we prefer to
choose accuracy over speed in this area.

-- PMM

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