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[PULL 17/19] hw/ppc: e500: Fill in correct <clock-frequency> for the ser
From: |
David Gibson |
Subject: |
[PULL 17/19] hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes |
Date: |
Wed, 10 Feb 2021 17:17:33 +1100 |
From: Bin Meng <bin.meng@windriver.com>
At present the <clock-frequency> property of the serial node is
populated with value zero. U-Boot's ns16550 driver is not happy
about this, so let's fill in a meaningful value.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1612362288-22216-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/e500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index c795276668..01517a6c6c 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -126,7 +126,7 @@ static void dt_serial_create(void *fdt, unsigned long long
offset,
qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
- qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
+ qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
--
2.29.2
- [PULL 05/19] ppc/pnv: Add trace events for PCI event notification, (continued)
- [PULL 05/19] ppc/pnv: Add trace events for PCI event notification, David Gibson, 2021/02/10
- [PULL 07/19] ppc/pnv: Use skiboot addresses to load kernel and ramfs, David Gibson, 2021/02/10
- [PULL 10/19] ppc/pnv: Remove default disablement of the PNOR contents, David Gibson, 2021/02/10
- [PULL 12/19] spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c, David Gibson, 2021/02/10
- [PULL 11/19] ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR, David Gibson, 2021/02/10
- [PULL 16/19] hw/ppc: e500: Use a macro for the platform clock frequency, David Gibson, 2021/02/10
- [PULL 18/19] hw/net: fsl_etsec: Reverse the RCTRL.RSF logic, David Gibson, 2021/02/10
- [PULL 19/19] target/ppc: Add E500 L2CSR0 write helper, David Gibson, 2021/02/10
- [PULL 13/19] spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper, David Gibson, 2021/02/10
- [PULL 15/19] ppc/pnv: Set default RAM size to 1 GB, David Gibson, 2021/02/10
- [PULL 17/19] hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes,
David Gibson <=
- Re: [PULL 00/19] ppc-for-6.0 queue 20210210, Peter Maydell, 2021/02/10