Re: [PATCH 4/5] target/ppc: Base changes to allow 32/64-bit insns

[Richard Henderson]

On 4/13/21 2:11 PM, Luis Pires wrote:
> @@ -7879,7 +7951,6 @@ static void ppc_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>   {
>       DisasContext *ctx = container_of(dcbase, DisasContext, base);
>       CPUPPCState *env = cs->env_ptr;
> -    int bound;
>   
>       ctx->exception = POWERPC_EXCP_NONE;
>       ctx->spr_cb = env->spr_cb;
> @@ -7961,8 +8032,7 @@ static void ppc_tr_init_disas_context(DisasContextBase 
> *dcbase, CPUState *cs)
>       msr_se = 1;
>   #endif
>   
> -    bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
> -    ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
> +    ctx->env = env;
>   }
>   

You've removed the logic that prevents translation from crossing a page 
boundary.  You need to replace it.

A good example of how to handle this properly is arm thumb, at the end of 
thumb_tr_translate_insn.

At the end of ppc_tr_translate_insn, you'd do something like

  if (dc->base.is_jmp == DISAS_NEXT
      && (dc->base.pc_next & (TARGET_PAGE_SIZE - 1))
         == (TARGET_PAGE_SIZE - 4)
      && ppc_peek_next_insn_size(ctx)) {
      dc->base.is_jmp = DISAS_TOO_MANY;
  }


r~