[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5
From: |
Cédric Le Goater |
Subject: |
[PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5 |
Date: |
Mon, 9 Aug 2021 15:45:40 +0200 |
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits have not been checked and performs the check
locally.
This configuration bit only applies to MSIs and LSIs are still checked
on the PHB to handle the assertion level.
PQ_disable enablement is a requirement for StoreEOI.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4_regs.h | 1 +
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c | 22 +++++++++++++++++++++-
hw/pci-host/pnv_phb4.c | 9 +++++++++
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/pnv_phb4_regs.h
b/include/hw/pci-host/pnv_phb4_regs.h
index 55df2c3e5ece..64f326b7158e 100644
--- a/include/hw/pci-host/pnv_phb4_regs.h
+++ b/include/hw/pci-host/pnv_phb4_regs.h
@@ -225,6 +225,7 @@
/* Fundamental register set B */
#define PHB_VERSION 0x800
#define PHB_CTRLR 0x810
+#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */
#define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)
#define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)
#define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index ef5992c6f05b..e0215c79e312 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -176,6 +176,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
*/
#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
+#define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits */
struct XiveSource {
DeviceState parent;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 7ac0c1816c86..633f3e5cd8f4 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -902,6 +902,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc,
uint32_t srcno)
}
}
+/*
+ * Sources can be configured with PQ offloading in which case the check
+ * on the PQ state bits of MSIs is disabled
+ */
+static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno)
+{
+ return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) &&
+ !xive_source_irq_is_lsi(xsrc, srcno);
+}
+
/*
* Returns whether the event notification should be forwarded.
*/
@@ -911,6 +921,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc,
uint32_t srcno)
assert(srcno < xsrc->nr_irqs);
+ if (xive_source_esb_disabled(xsrc, srcno)) {
+ return true;
+ }
+
ret = xive_esb_trigger(&xsrc->status[srcno]);
if (xive_source_irq_is_lsi(xsrc, srcno) &&
@@ -931,6 +945,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t
srcno)
assert(srcno < xsrc->nr_irqs);
+ if (xive_source_esb_disabled(xsrc, srcno)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n",
srcno);
+ return false;
+ }
+
ret = xive_esb_eoi(&xsrc->status[srcno]);
/*
@@ -952,9 +971,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t
srcno)
static void xive_source_notify(XiveSource *xsrc, int srcno)
{
XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive);
+ bool pq_checked = !xive_source_esb_disabled(xsrc, srcno);
if (xnc->notify) {
- xnc->notify(xsrc->xive, srcno, true);
+ xnc->notify(xsrc->xive, srcno, pq_checked);
}
}
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 3edd5845ebde..cf506d1623c3 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -475,6 +475,15 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
flags = 0;
}
+ /*
+ * When the PQ disable configuration bit is set, the check on the
+ * PQ state bits is disabled on the PHB side (for MSI only) and it
+ * is performed on the IC side instead.
+ */
+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) {
+ flags |= XIVE_SRC_PQ_DISABLE;
+ }
+
phb->xsrc.esb_shift = shift;
phb->xsrc.esb_flags = flags;
--
2.31.1
- Re: [PATCH 15/26] ppc/pnv: Add a HOMER model to POWER10, (continued)
- [PATCH 16/26] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10), Cédric Le Goater, 2021/08/09
- [PATCH 22/26] ppc/pnv: add XIVE Gen2 TIMA support, Cédric Le Goater, 2021/08/09
- [PATCH 11/26] ppc/pnv: Add a XIVE2 controller to the POWER10 chip., Cédric Le Goater, 2021/08/09
- [PATCH 12/26] ppc/pnv: Add a OCC model for POWER10, Cédric Le Goater, 2021/08/09
- [PATCH 18/26] ppc/xive: Add support for PQ state bits offload, Cédric Le Goater, 2021/08/09
- [PATCH 10/26] ppc/xive2: Introduce a presenter matching routine, Cédric Le Goater, 2021/08/09
- [PATCH 19/26] ppc/pnv: Add support for PQ offload on PHB5,
Cédric Le Goater <=
- [PATCH 21/26] pnv/xive2: Introduce new capability bits, Cédric Le Goater, 2021/08/09
- [PATCH 17/26] ppc/xive2: Add support for notification injection on ESB pages, Cédric Le Goater, 2021/08/09
- [PATCH 23/26] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1), Cédric Le Goater, 2021/08/09
- [PATCH 26/26] pnv/xive2: Add support for 8bits thread id, Cédric Le Goater, 2021/08/09
- [PATCH 24/26] xive2: Add a get_config() handler for the router configuration, Cédric Le Goater, 2021/08/09
- [PATCH 25/26] pnv/xive2: Add support for automatic save&restore, Cédric Le Goater, 2021/08/09
- [PATCH 20/26] ppc/pnv: Add support for PHB5 "Address-based trigger" mode, Cédric Le Goater, 2021/08/09
- Re: [PATCH 00/26] ppc/pnv: Extend the powernv10 machine, David Gibson, 2021/08/10
- Re: [PATCH 00/26] ppc/pnv: Extend the powernv10 machine, David Gibson, 2021/08/10