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Re: [PATCH for-6.2 v2 2/2] target/ppc: fix vector registers access in gd


From: Peter Maydell
Subject: Re: [PATCH for-6.2 v2 2/2] target/ppc: fix vector registers access in gdbstub for little-endian
Date: Thu, 19 Aug 2021 13:57:38 +0100

On Wed, 18 Aug 2021 at 12:11, <matheus.ferst@eldorado.org.br> wrote:
>
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> As vector registers are stored in host endianness, we shouldn't swap its
> 64-bit elements in user mode. Add a 16-byte case in
> ppc_maybe_bswap_register to handle the reordering of elements in softmmu
> and remove avr_need_swap which is now unused.
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
>  target/ppc/gdbstub.c | 32 +++++++-------------------------
>  1 file changed, 7 insertions(+), 25 deletions(-)
> @@ -486,14 +479,9 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArray 
> *buf, int n)
>
>      if (n < 32) {
>          ppc_avr_t *avr = cpu_avr_ptr(env, n);
> -        if (!avr_need_swap(env)) {
> -            gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
> -        } else {
> -            gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
> -        }
> +        gdb_get_reg128(buf, avr->VsrD(0) , avr->VsrD(1));

Stray space before comma.

Otherwise if we first fix up the Int128 field order then:
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM



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