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[PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers
From: |
David Gibson |
Subject: |
[PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers |
Date: |
Fri, 27 Aug 2021 17:09:44 +1000 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
These helpers shouldn't depend on the host endianness, as they only use
shifts, ands, and int128_* methods.
Fixes: 60caf2216bf0 ("target-ppc: add vextu[bhw][lr]x instructions")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826141446.2488609-3-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/int_helper.c | 38 ++++++++++----------------------------
1 file changed, 10 insertions(+), 28 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index efa833ef64..c2d3248d1e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1492,34 +1492,16 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *b)
}
}
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VEXTU_X_DO(name, size, left) \
- target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
- { \
- int index; \
- if (left) { \
- index = (a & 0xf) * 8; \
- } else { \
- index = ((15 - (a & 0xf) + 1) * 8) - size; \
- } \
- return int128_getlo(int128_rshift(b->s128, index)) & \
- MAKE_64BIT_MASK(0, size); \
- }
-#else
-#define VEXTU_X_DO(name, size, left) \
- target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
- { \
- int index; \
- if (left) { \
- index = ((15 - (a & 0xf) + 1) * 8) - size; \
- } else { \
- index = (a & 0xf) * 8; \
- } \
- return int128_getlo(int128_rshift(b->s128, index)) & \
- MAKE_64BIT_MASK(0, size); \
- }
-#endif
-
+#define VEXTU_X_DO(name, size, left) \
+target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+{ \
+ int index = (a & 0xf) * 8; \
+ if (left) { \
+ index = 128 - index - size; \
+ } \
+ return int128_getlo(int128_rshift(b->s128, index)) & \
+ MAKE_64BIT_MASK(0, size); \
+}
VEXTU_X_DO(vextublx, 8, 1)
VEXTU_X_DO(vextuhlx, 16, 1)
VEXTU_X_DO(vextuwlx, 32, 1)
--
2.31.1
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, (continued)
- [PULL 07/18] ppc: Add a POWER10 DD2 CPU, David Gibson, 2021/08/27
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, David Gibson, 2021/08/27
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines, David Gibson, 2021/08/27
- [PULL 12/18] ppc/pnv: add a chip topology index for POWER10, David Gibson, 2021/08/27
- [PULL 11/18] ppc/pnv: Distribute RAM among the chips, David Gibson, 2021/08/27
- [PULL 06/18] ppc/pnv: update skiboot to commit 820d43c0a775., David Gibson, 2021/08/27
- [PULL 17/18] include/qemu/int128.h: introduce bswap128s, David Gibson, 2021/08/27
- [PULL 14/18] ppc/xive: Export xive_presenter_notify(), David Gibson, 2021/08/27
- [PULL 15/18] include/qemu/int128.h: define struct Int128 according to the host endianness, David Gibson, 2021/08/27
- [PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers,
David Gibson <=
- [PULL 18/18] target/ppc: fix vector registers access in gdbstub for little-endian, David Gibson, 2021/08/27
- Re: [PULL 00/18] ppc-for-6.2 queue 20210827, Peter Maydell, 2021/08/28